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P. W. Chandana Prasad:
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Publications of Author
 P. W. Chandana Prasad, Ali Assi, Mohamed Raseen
BDD Minimization Using Graph Parameter Permutation. [Citation Graph (0, 0)][DBLP] ESA/VLSI, 2004, pp:491496 [Conf]
 P. W. Chandana Prasad, Bruce Mills, Ali Assi, S. M. N. Arosha Senanayake, V. C. Prasad
Evaluation time Estimation for Pass Transistor Logic circuits. [Citation Graph (0, 0)][DBLP] DELTA, 2006, pp:422428 [Conf]
 P. W. Chandana Prasad, M. Maria Dominic, Ashutosh Kumar Singh
Improved Variable Ordering for ROBDDs. [Citation Graph (0, 0)][DBLP] ICADL, 2003, pp:544547 [Conf]
 P. W. Chandana Prasad, M. Maria Dominic, Ashutosh Kumar Singh
Variable Order Verification Use of Logic Representation. [Citation Graph (0, 0)][DBLP] ICADL, 2003, pp:689 [Conf]
 P. W. Chandana Prasad, Ali Assi, Mohamed Raseen, A. Harb
BDD Based Method for Fast Equivalence Checking. [Citation Graph (0, 0)][DBLP] International Conference on Computational Intelligence, 2004, pp:474477 [Conf]
 Mohamed Raseen, Ali Assi, P. W. Chandana Prasad, A. Harb
Effect of Boolean Minterms on the Complexity of ROBDDs. [Citation Graph (0, 0)][DBLP] International Conference on Computational Intelligence, 2004, pp:454457 [Conf]
 Bruce Mills, P. W. Chandana Prasad, Ali Assi
Formal Presentation of Two Initial Variable Ordering Algorithms for Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP] MSV, 2006, pp:256262 [Conf]
 Mohamed Raseen, P. W. Chandana Prasad, Ali Assi
An efficient estimation of the ROBDD's complexity. [Citation Graph (0, 0)][DBLP] Integration, 2006, v:39, n:3, pp:211228 [Journal]
 P. W. Chandana Prasad, Ali Assi, Azam Beg
Binary Decision Diagrams and neural networks. [Citation Graph (0, 0)][DBLP] The Journal of Supercomputing, 2007, v:39, n:3, pp:301320 [Journal]
Utilizing synthesis to verify Boolean function models. [Citation Graph (, )][DBLP]
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