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Valery Sklyarov: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Valery Sklyarov, Iouliia Skliarova
    Design of Digital Circuits on the Basis of Hardware Templates. [Citation Graph (0, 0)][DBLP]
    Embedded Systems and Applications, 2003, pp:56-62 [Conf]
  2. Arnaldo Oliveira, Valery Sklyarov, António de Brito Ferrari
    ARPA - A Technology Independent and Synthetizable System-on-Chip Model for Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:484-491 [Conf]
  3. Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida
    Design Tools and Reusable Libraries for FPGA-Based Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:255-263 [Conf]
  4. Valery Sklyarov, Iouliia Skliarova, Arnaldo Oliveira, António de Brito Ferrari
    A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:222-229 [Conf]
  5. Valery Sklyarov, Iouliia Skliarova
    Architecture of a Reconfigurable Processor for Implementing Search Algorithm over Discrete Matrices. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:127-133 [Conf]
  6. Valery Sklyarov, Nuno Lau, Ricardo Sal Monteiro, Andreia Melo, Arnaldo Oliveira, Konstantin Kondratjuk
    Design of Virtual Digital Controllers Based on Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10200-10203 [Conf]
  7. Valery Sklyarov, J. Fonseca, Ricardo Sal Monteiro, Arnaldo Oliveira, Andreia Melo, Nuno Lau, Iouliia Skliarova, P. Neves, António de Brito Ferrari
    Development System for FPGA-Based Digital Circuits. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:266-267 [Conf]
  8. Valery Sklyarov, J. Fonseca, Ricardo Sal Monteiro, Arnaldo Oliveira, Andreia Melo, Nuno Lau, Konstantin Kondratjuk, Iouliia Skliarova, P. Neves, António de Brito Ferrari
    FPGA-Targeted Development System for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:248- [Conf]
  9. Arnaldo Oliveira, Andreia Melo, Valery Sklyarov
    Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:313-322 [Conf]
  10. Valery Sklyarov, Ricardo Sal Monteiro, Nuno Lau, Andreia Melo, Arnaldo Oliveira, Konstantin Kondratjuk
    Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:19-28 [Conf]
  11. Valery Sklyarov, Iouliia Skliarova
    Reconfigurable Systems in Education. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1020-1023 [Conf]
  12. Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida
    High-Level Design Tools for FPGA-Based Combinatorial Accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:976-979 [Conf]
  13. Valery Sklyarov, Iouliia Skliarova, Bruno S. Pimentel
    FPGA-based implementation and comparison of recursive and iterative algorithms. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:235-240 [Conf]
  14. Valery Sklyarov, Iouliia Skliarova, Bruno S. Pimentel, Joel Arrais
    Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:922-926 [Conf]
  15. Valery Skylarov
    Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:718-728 [Conf]
  16. Valery Sklyarov
    An Evolutionary Algorithm for the Synthesis of RAM-Based FSMs. [Citation Graph (0, 0)][DBLP]
    IEA/AIE, 2002, pp:108-118 [Conf]
  17. Nuno Lau, Valery Sklyarov
    Dynamically Reconfigurable Implementation of Control Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:137-148 [Conf]
  18. Valery Sklyarov, Iouliia Skliarova
    Evolutionary Algorithm for State Encoding. [Citation Graph (0, 0)][DBLP]
    IFIP AI, 2006, pp:227-236 [Conf]
  19. Valery Sklyarov, Iouliia Skliarova
    Recursive and Iterative Algorithms for N-ary Search Problems. [Citation Graph (0, 0)][DBLP]
    IFIP PPAI, 2006, pp:81-90 [Conf]
  20. Valery Sklyarov, Iouliia Skliarova
    E-learning Tools and Web-resources for Teaching Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    Education for the 21st Century, 2006, pp:215-224 [Conf]
  21. Valery Sklyarov
    Graphical Description and Hardware Implementation of Parallel Control Algorithms. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1390-1396 [Conf]
  22. Arkadij Zakrevskij, Valery Sklyarov
    The Specification and Design of Parallel Logical Control Devices. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  23. Valery Sklyarov
    Hardware/software modeling of FPGA-based systems. [Citation Graph (0, 0)][DBLP]
    Parallel Algorithms Appl., 2002, v:17, n:1, pp:19-39 [Journal]
  24. Valery Sklyarov
    FPGA-based implementation of recursive algorithms. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:197-211 [Journal]
  25. Iouliia Skliarova, Valery Sklyarov
    Software/Configware Implementation of Combinatorial Algorithms. [Citation Graph (0, 0)][DBLP]
    AICCSA, 2007, pp:539-546 [Conf]
  26. Valery Sklyarov, Iouliia Skliarova
    Encoding Algorithms for Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    AICCSA, 2007, pp:359-366 [Conf]
  27. Valery Sklyarov, Iouliia Skliarova
    Reuse Technique in Hardware Design. [Citation Graph (0, 0)][DBLP]
    IRI, 2007, pp:36-41 [Conf]
  28. Valery Sklyarov, Iouliia Skliarova, Manuel Almeida, Bruno S. Pimentel
    A prototyping system for mobile devices. [Citation Graph (0, 0)][DBLP]
    IWCMC, 2007, pp:505-510 [Conf]
  29. Valery Sklyarov
    Hierarchical finite-state machines and their use for digital control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:222-228 [Journal]

  30. Recursion in reconfigurable computing: A survey of implementation approaches. [Citation Graph (, )][DBLP]


  31. Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware. [Citation Graph (, )][DBLP]


  32. Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable Systems. [Citation Graph (, )][DBLP]


  33. Multimedia Tools for Teaching Reconfigurable Systems. [Citation Graph (, )][DBLP]


  34. Reconfigurable Systems and their Influence on Mobile and Multimedia Applications. [Citation Graph (, )][DBLP]


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