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Scott C. Smith: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bonita Bhaskaran, Venkat Satagopan, Waleed Al-Assadi, Scott Smith
    Implementation of Design For Test for Asynchronous NCL Designs. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:78-84 [Conf]
  2. Bonita Bhaskaran, Venkat Satagopan, Scott Smith
    High-Speed Energy Estimation for Delay-Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:35-41 [Conf]
  3. Anshul Singh, Scott Smith
    Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:115-121 [Conf]
  4. Scott C. Smith
    Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:407-412 [Conf]
  5. Scott C. Smith
    Design of a NULL Convention Self-Timed Divider. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:447-453 [Conf]
  6. Scott C. Smith
    Design of a logic element for implementing an asynchronous FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:13-22 [Conf]
  7. Scott C. Smith
    Speedup of Self-Timed Digital Systems Using Early Completion. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:107-116 [Conf]
  8. Satish K. Bandapati, Scott C. Smith
    Design and Characterization of NULL Convention Arithmetic Logic Units. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:178-184 [Conf]
  9. Scott C. Smith
    Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:143-149 [Conf]
  10. Satish K. Bandapati, Scott C. Smith, Minsu Choi
    Design and Characterization of Null Convention Self-Timed Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:6, pp:26-36 [Journal]
  11. Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, D. Ferguson, D. Lamb
    Optimization of NULL convention self-timed circuits. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:37, n:3, pp:135-165 [Journal]
  12. Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, M. Hagedorn, D. Ferguson
    Delay-insensitive gate-level pipelining. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:30, n:2, pp:103-131 [Journal]
  13. Scott C. Smith
    Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:672-683 [Journal]

  14. Delay-Insensitive Ternary Logic. [Citation Graph (, )][DBLP]


  15. Particle Swarm Optimization: A Hardware Implementation. [Citation Graph (, )][DBLP]


  16. Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. [Citation Graph (, )][DBLP]


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