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Publications of Author

1. Hamid R. Zarandi, Seyed Ghassem Miremadi, Shaahin Hessabi, Ali Reza Ejlali
   A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models. [Citation Graph (0, 0)][DBLP]
   ESA/VLSI, 2004, pp:582-588 [Conf]
   
2. Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali
   Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. [Citation Graph (0, 0)][DBLP]
   DFT, 2003, pp:485-492 [Conf]
   
3. Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi
   A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. [Citation Graph (0, 0)][DBLP]
   DSN, 2003, pp:479-0 [Conf]
   
4. Hamid R. Zarandi, Seyed Ghassem Miremadi
   Hierarchical Multiple Associative Mapping in Cache Memories. [Citation Graph (0, 0)][DBLP]
   ECBS, 2005, pp:95-101 [Conf]
   
5. Hamid R. Zarandi, Seyed Ghassem Miremadi, Hamid Sarbazi-Azad
   Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2004, pp:101-108 [Conf]
   
6. Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali
   Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems. [Citation Graph (0, 0)][DBLP]
   ISPDC, 2003, pp:281-0 [Conf]
   
7. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
   SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
   ISQED, 2007, pp:380-385 [Conf]
   
8. Hamid R. Zarandi, Seyed Ghassem Miremadi
   Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme. [Citation Graph (0, 0)][DBLP]
   LADC, 2005, pp:121-130 [Conf]
   
9. Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali
   Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
   PRDC, 2004, pp:327-332 [Conf]
   
10. Hamid R. Zarandi, Seyed Ghassem Miremadi
    A Highly Fault Detectable Cache Architecture for Dependable Computing. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 2004, pp:45-59 [Conf]
    
11. Hamid R. Zarandi, Seyed Ghassem Miremadi
    A fault-tolerant cache architecture based on binary set partitioning. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:1, pp:86-99 [Journal]
    
12. Hamid R. Zarandi, Seyed Ghassem Miremadi
    Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:2-3, pp:461-470 [Journal]
    
13. Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
    Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
    
14. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
    CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3675-3678 [Conf]
    
15. Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan
    Multiple Upsets Tolerance in SRAM Memory. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:365-368 [Conf]
    
16. Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
    CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3696-3699 [Conf]
    
17. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
    Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:141-144 [Conf]
    
18. 
    An Analysis of Fault Effects and Propagations in AVR Microcontroller ATmega103(L). [Citation Graph (, )][DBLP]
    
    
19. 
    Analysis of Transient Faults on a MIPS-Based Dual-Core Processor. [Citation Graph (, )][DBLP]
    
    
20. 
    An Adaptive Redundancy Oriented Method to Tolerate Soft Errors in SRAM-Based FPGAs Using Unused Resources. [Citation Graph (, )][DBLP]
    
    
21. 
    A Fault Injection Attitude based on Background Debug Mode in Embedded Systems. [Citation Graph (, )][DBLP]
    
    
22. 
    Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. [Citation Graph (, )][DBLP]
    
    
23. 
    Fault injection-based evaluation of a synchronous NoC router. [Citation Graph (, )][DBLP]
    
    
24. 
    Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation. [Citation Graph (, )][DBLP]
    
    
25. 
    Investigation of Transient Fault Effects in an Asynchronous NoC Router. [Citation Graph (, )][DBLP]
    
    
26. 
    A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs. [Citation Graph (, )][DBLP]