The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Xue-mi Zhao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xue-mi Zhao, Zhiying Wang
    Power Optimization of Interconnection Networks for Transport Triggered Architecture. [Citation Graph (0, 0)][DBLP]
    ESA, 2006, pp:154-159 [Conf]
  2. Jiang-chun Ren, Kui Dai, Zhiying Wang, Xue-mi Zhao, Yuan-man Tong
    Design and Implementation a TPM Chip SUP320 by SOC. [Citation Graph (0, 0)][DBLP]
    SEC, 2005, pp:143-154 [Conf]
  3. Yong Li, Zhiying Wang, Xue-mi Zhao, Jian Ruan, Kui Dai
    Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:354-363 [Conf]
  4. Xue-mi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai
    A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:216-221 [Conf]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002