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Publications of Author

1. Xiang Gao, Terrance E. Boult, Frans Coetzee, Visvanathan Ramesh
   Error Analysis of Background Adaption. [Citation Graph (0, 0)][DBLP]
   CVPR, 2000, pp:1503-1510 [Conf]
   
2. Weiliang Li, Xiang Gao, Ying Zhu, Visvanathan Ramesh, Terrance E. Boult
   On the Small Sample Performance of Boosted Classifiers. [Citation Graph (0, 0)][DBLP]
   CVPR (2), 2005, pp:574-581 [Conf]
   
3. Benedicte Bascle, Xiang Gao, Visvanathan Ramesh
   Parametric and Non-parametric Methods for Linear Extraction. [Citation Graph (0, 0)][DBLP]
   ECCV Workshop SMVP, 2004, pp:175-186 [Conf]
   
4. Xiang Gao, Visvanathan Ramesh, Terrance E. Boult
   Statistical Characterization of Morphological Operator Sequences. [Citation Graph (0, 0)][DBLP]
   ECCV (4), 2002, pp:590-605 [Conf]
   
5. Feng Bao, Robert H. Deng, Xiang Gao, Yoshihide Igarashi
   Modified Finite Automata Public Key Cryptosystem. [Citation Graph (0, 0)][DBLP]
   ISW, 1997, pp:82-95 [Conf]
   
6. Xiang Gao, Jian Yang, Mike P. Papazoglou
   The Capability Matching of Web Services. [Citation Graph (0, 0)][DBLP]
   ISMSE, 2002, pp:56-63 [Conf]
   
7. Guanghui Wang, Shewei Wang, Xiang Gao, Yubing Li
   Three Dimensional Reconstruction of Structured Scenes Based on Vanishing Points. [Citation Graph (0, 0)][DBLP]
   PCM, 2006, pp:935-942 [Conf]
   
8. Xiang Gao, Kent Vander Velden, Daniel F. Voytas, Xun Gu
   SplitTester: software to identify domains responsible for functional divergence in protein family. [Citation Graph (0, 0)][DBLP]
   BMC Bioinformatics, 2005, v:6, n:, pp:137- [Journal]
   
9. Terrance E. Boult, Xiang Gao, Ross J. Micheals, Michael Eckmann
   Omni-directional visual surveillance. [Citation Graph (0, 0)][DBLP]
   Image Vision Comput., 2004, v:22, n:7, pp:515-534 [Journal]
   
10. Xiang Gao, Eric A. M. Klumperink, Bram Nauta
    Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2854-2857 [Conf]
    
11. 
    A general method to make multi-clock system deterministic. [Citation Graph (, )][DBLP]
    
    
12. 
    A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only). [Citation Graph (, )][DBLP]
    
    
13. 
    Barrier Optimization for OpenMP Program. [Citation Graph (, )][DBLP]
    
    
14. 
    Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. [Citation Graph (, )][DBLP]
    
    
15. 
    Anonymous ID Signature Scheme with Provable Identity. [Citation Graph (, )][DBLP]
    
    
16. 
    Resource Allocation for OFDM Systems in the Presence of Time-Varying Channels. [Citation Graph (, )][DBLP]
    
    
17. 
    An Enhanced HyperTransport Controller with Cache Coherence Support for Multiple-CMP. [Citation Graph (, )][DBLP]
    
    
18. 
    Efficiency-Aware QoS DRAM Scheduler. [Citation Graph (, )][DBLP]