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T. Watanabe: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jie Huang, K. Kume, A. Saji, M. Nishihashi, T. Watanabe, William L. Martens
    Robotic Spatial Sound Localization and Its 3-D Sound Human Interface. [Citation Graph (0, 0)][DBLP]
    CW, 2002, pp:191-200 [Conf]
  2. T. Watanabe, T. Masuishi, T. Nishiyama, N. Horie
    Knowledge-based optimal IIL generator from conventional logic circuit descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:608-614 [Conf]
  3. K. Murano, Hideo Kuwahara, T. Watanabe, K. Ohta, H. Gambe, T. Gotohda, H. Takaoka
    A Processor VLSI for Multiplexing and Circuit Termination Functions - MUX Processor. [Citation Graph (0, 0)][DBLP]
    ICC, 1986, pp:1674-1678 [Conf]
  4. C. Jittawiriyanukoon, T. Watanabe, H. Nakanishi, Yoshikazu Tezuka
    Approximate Analytic Method for Computer Systems with Multiple Level Concurrent Programs. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1989, pp:82-90 [Conf]
  5. T. Watanabe, H. Asai
    Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:266-269 [Conf]
  6. A. Kamo, T. Watanabe, H. Asai
    Expanded GMC for transient analysis of transmission line networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:33-36 [Conf]
  7. E. Miuno, T. Abaashi, T. Watanabe
    Extracting nonplanar connections in a terminal-vertex graph. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:121-124 [Conf]
  8. M. Yamauchi, T. Watanabe
    A heuristic algorithm SDS for scheduling with timed Petri nets. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:81-84 [Conf]
  9. H. Kubota, A. Kamo, T. Watanabe, H. Asai
    Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:649-552 [Conf]
  10. I. Hattori, A. Kamo, T. Watanabe, H. Asai
    Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:29-32 [Conf]
  11. T. Watanabe, Makoto Endo, N. Miyahara
    A New Automatic Logic Interconnection Verification System for VLSI Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:70-82 [Journal]
  12. T. Watanabe, H. Kitazawa, Y. Sugiyama
    A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:2, pp:241-250 [Journal]
  13. T. Watanabe, A. Mori
    RORP: Distributed object relocation protocol for wide area networks. [Citation Graph (0, 0)][DBLP]
    IPCCC, 1999, pp:217-224 [Conf]
  14. T. Watanabe, S. G. Monanty
    On an inclusion-exclusion formula based on the reflection principle. [Citation Graph (0, 0)][DBLP]
    Discrete Mathematics, 1987, v:64, n:2-3, pp:281-288 [Journal]

  15. Fuzzy auto-regressive model and its applications. [Citation Graph (, )][DBLP]

  16. High density bit-serial FPGA with LUT embedding shift register function. [Citation Graph (, )][DBLP]

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