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Muhammad M. Khellah: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
    Variations-aware low-power design with voltage scaling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:529-534 [Conf]
  2. A. M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry
    A Low-Power High-Performance Embedded SRAM Macrocell. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:13-17 [Conf]
  3. Muhammad M. Khellah, Mohamed I. Elmasry
    Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:414-419 [Conf]
  4. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De
    Serial-link bus: a low-power on-chip bus architecture. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:541-546 [Conf]
  5. Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
    A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:253-257 [Conf]
  6. Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De
    Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:592-595 [Conf]
  7. Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
    Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:79-84 [Conf]
  8. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
    Reducing the Data Switching Activity on Serial Link Buses. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:425-432 [Conf]
  9. Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic
    Minimizing FPGA Interconnect Delays. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:16-23 [Journal]
  10. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De
    Formal derivation of optimal active shielding for low-power on-chip buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:821-836 [Journal]
  11. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
    Reducing the data switching activity of serialized datastreams. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  12. Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De
    Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  13. Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
    Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:746-757 [Journal]
  14. Muhammad M. Khellah, Mohamed I. Elmasry
    A low-power high-performance current-mode multiport SRAM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:590-598 [Journal]

  15. Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. [Citation Graph (, )][DBLP]


  16. Resilient microprocessor design for high performance & energy efficiency. [Citation Graph (, )][DBLP]


  17. Analytical Model for the Propagation Delay of Through Silicon Vias. [Citation Graph (, )][DBLP]


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