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Vivek De: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
    Variations-aware low-power design with voltage scaling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:529-534 [Conf]
  2. Shekhar Borkar, Tanay Karnik, Vivek De
    Design and reliability challenges in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:75- [Conf]
  3. Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De
    Parameter variations and impact on circuits and microarchitecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:338-342 [Conf]
  4. Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
    Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:486-491 [Conf]
  5. Pankaj Pant, Vivek De, Abhijit Chatterjee
    Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:403-408 [Conf]
  6. George Sery, Shekhar Borkar, Vivek De
    Life is CMOS: why chase the life after? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:78-83 [Conf]
  7. Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De
    Dynamic noise analysis in precharge-evaluate circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:243- [Conf]
  8. James Tschanz, Keith A. Bowman, Vivek De
    Variation-tolerant circuits: circuit solutions and techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:762-763 [Conf]
  9. Arman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
    Design optimizations for microprocessors at low temperature. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:2-5 [Conf]
  10. Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De
    Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:489-494 [Conf]
  11. Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
    Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:430-435 [Conf]
  12. Wei Zhang 0002, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De
    Compiler Support for Reducing Leakage Energy Consumption. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11146-11147 [Conf]
  13. Vivek De, Shekhar Borkar
    Low power and high performance design challenges in future technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:1-6 [Conf]
  14. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De
    Serial-link bus: a low-power on-chip bus architecture. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:541-546 [Conf]
  15. Tanay Karnik, Shekhar Borkar, Vivek De
    Sub-90nm technologies: challenges and opportunities for CAD. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:203-206 [Conf]
  16. Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge
    Total power-optimal pipelining and parallel processing under process variations in nanometer technology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:535-540 [Conf]
  17. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De
    A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:567-573 [Conf]
  18. Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De
    Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:592-595 [Conf]
  19. Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra
    Cascode buffer for monolithic voltage conversion operating at high input supply voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:464-467 [Conf]
  20. James Tschanz, Siva Narendra, Ali Keshavarzi, Vivek De
    Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:9-12 [Conf]
  21. Vivek De, Shekhar Borkar
    Technology and design challenges for low power and high performance. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:163-168 [Conf]
  22. Vivek De, James D. Meindl
    A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:371-375 [Conf]
  23. Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl
    Circuit techniques for low-power CMOS GSI. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:193-196 [Conf]
  24. Ali Keshavarzi, Sean Ma, Siva Narendra, B. Bloechel, K. Mistry, T. Ghani, Shekhar Borkar, Vivek De
    Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:207-212 [Conf]
  25. Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
    Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:252-254 [Conf]
  26. Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De
    Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:26-29 [Conf]
  27. Siva Narendra, Vivek De, Dimitri Antoniadis, Anantha Chandrakasan, Shekhar Borkar
    Scaling of stack effect and its application for leakage reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:195-200 [Conf]
  28. Siva Narendra, Vivek De, Shekhar Borkar, Dimitri Antoniadis, Anantha Chandrakasan
    Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:19-23 [Conf]
  29. Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald Gardner, Siva Narendra, Tanay Karnik, Vivek De
    Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:263-268 [Conf]
  30. Xinghai Tang, Vivek De, James D. Meindl
    Effects of random MOSFET parameter fluctuations on total power consumption. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:233-236 [Conf]
  31. Stephen Tang, Siva Narendra, Vivek De
    Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:199-204 [Conf]
  32. James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
    Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:147-152 [Conf]
  33. Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
    Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:79-84 [Conf]
  34. Vivek De
    Leakage-tolerant design techniques for high performance processors. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:28-28 [Conf]
  35. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
    Reducing the Data Switching Activity on Serial Link Buses. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:425-432 [Conf]
  36. Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman
    Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:279-0 [Conf]
  37. Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman
    High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:517-521 [Conf]
  38. Ron Wilson, Siva Narendra, Vivek De
    Evening Panel Discussion: Process Variation: Is It Too Much to Handle? [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:213-0 [Conf]
  39. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, K. Soumyanath, Vivek De
    Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1051-1059 [Conf]
  40. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak
    Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:606-612 [Conf]
  41. Liqiong Wei, Kaushik Roy, Vivek De
    Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:24-29 [Conf]
  42. Jaume Segura, Vivek De, Ali Keshavarzi
    Challenges in Nanometric Technology Scaling: Trends and Projections. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:447-448 [Conf]
  43. Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
    Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:36-43 [Journal]
  44. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De
    Formal derivation of optimal active shielding for low-power on-chip buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:821-836 [Journal]
  45. Volkan Kursun, Vivek De, Eby G. Friedman, Siva G. Narendra
    Monolithic voltage conversion in low-voltage CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:9, pp:863-867 [Journal]
  46. Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James Tschanz, Vivek De
    Comparative Analysis of Conventional and Statistical Design Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:238-243 [Conf]
  47. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
    Reducing the data switching activity of serialized datastreams. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  48. Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De
    Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  49. Osman S. Unsal, James Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin
    Impact of Parameter Variations on Circuits and Microarchitecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:6, pp:30-39 [Journal]
  50. Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
    Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:746-757 [Journal]
  51. Xinghai Tang, Vivek De, James D. Meindl
    Intrinsic MOSFET parameter fluctuations due to random dopant placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:369-376 [Journal]
  52. Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
    Design and optimization of dual-threshold circuits for low-voltage low-power applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:16-24 [Journal]
  53. Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, M. Stan, Vivek De
    Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:91-95 [Journal]
  54. Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman
    Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:514-522 [Journal]
  55. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De
    Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:863-870 [Journal]
  56. Vivek De, Luca Benini
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:753-754 [Journal]

  57. Circuit techniques for dynamic variation tolerance. [Citation Graph (, )][DBLP]


  58. Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. [Citation Graph (, )][DBLP]


  59. Resilient microprocessor design for high performance & energy efficiency. [Citation Graph (, )][DBLP]


  60. Analytical Model for the Propagation Delay of Through Silicon Vias. [Citation Graph (, )][DBLP]


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