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Sudhakar Bobba: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
DAC, 2001, pp:295-300 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
High-performance bidirectional repeaters. [Citation Graph (0, 0)][DBLP]
ACM Great Lakes Symposium on VLSI, 2000, pp:53-58 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
Maximum Current Estimation in Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
Great Lakes Symposium on VLSI, 1998, pp:301-306 [Conf] - Sudhakar Bobba, Tyler Thorp, Kathirgamar Aingaran, Dean Liu
IC Power Distribution Challenges. [Citation Graph (0, 0)][DBLP]
ICCAD, 2001, pp:643-650 [Conf] - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
Simulation and Optimization of the Power Distribution Network in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
ICCAD, 2000, pp:481-486 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
Current-Mode Threshold Logic Gates. [Citation Graph (0, 0)][DBLP]
ICCD, 2000, pp:235-240 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits. [Citation Graph (0, 0)][DBLP]
ISCAS (5), 2001, pp:195-198 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
Maximum voltage variation in the power distribution network of VLSI circuits with RLC models. [Citation Graph (0, 0)][DBLP]
ISLPED, 2001, pp:376-381 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
Estimation of maximum current envelope for power bus analysis and design. [Citation Graph (0, 0)][DBLP]
ISPD, 1998, pp:141-146 [Conf] - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
Power Bus Maximum Voltage Drop in Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP]
ISQED, 2000, pp:263-268 [Conf] - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP]
ISQED, 2001, pp:205-210 [Conf] - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP]
ISQED, 2001, pp:257-0 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag
Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. [Citation Graph (0, 0)][DBLP]
VLSI Design, 1999, pp:358-0 [Conf]
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