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## Search the dblp DataBase
Ibrahim N. Hajj:
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## Publications of Author- Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
**Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:295-300 [Conf] - Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
**Post-route gate sizing for crosstalk noise reduction.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:954-957 [Conf] - Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj
**Diagnosis and Correction of Logic Design Errors in Digital Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 1993, pp:503-508 [Conf] - Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
**Maximum Current Estimation in CMOS Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 1992, pp:2-7 [Conf] - Harish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj
**Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 1993, pp:384-388 [Conf] - Farid N. Najm, Shashank Goel, Ibrahim N. Hajj
**Power Estimation in Sequential Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 1995, pp:635-640 [Conf] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Analytical Estimation of Transition Activity From Word-Level Signal Statistics.**[Citation Graph (0, 0)][DBLP] DAC, 1997, pp:582-587 [Conf] - Daniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj
**Delay Modeling and Time of Bipolar Digital Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 1988, pp:288-293 [Conf] - Georgios I. Stamoulis, Ibrahim N. Hajj
**Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects.**[Citation Graph (0, 0)][DBLP] DAC, 1993, pp:379-383 [Conf] - Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj
**Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .**[Citation Graph (0, 0)][DBLP] DATE, 2002, pp:456-464 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
**High-performance bidirectional repeaters.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2000, pp:53-58 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
**Maximum Current Estimation in Programmable Logic Arrays.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1998, pp:301-306 [Conf] - Ninglong Lu, Ibrahim N. Hajj
**An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1999, pp:68-0 [Conf] - Andreas G. Veneris, Ibrahim N. Hajj
**A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1997, pp:45-50 [Conf] - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
**Simulation and Optimization of the Power Distribution Network in VLSI Circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 2000, pp:481-486 [Conf] - Tzuhao Chen, Ibrahim N. Hajj
**GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:555-561 [Conf] - Weitong Chuang, Ibrahim N. Hajj
**Delay and area optimization for compact placement by gate resizing and relocation.**[Citation Graph (0, 0)][DBLP] ICCAD, 1994, pp:145-148 [Conf] - Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
**A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area.**[Citation Graph (0, 0)][DBLP] ICCAD, 1993, pp:220-223 [Conf] - Ibrahim N. Hajj
**An Algebra for Switch-Level Simulation.**[Citation Graph (0, 0)][DBLP] ICCAD, 1990, pp:488-491 [Conf] - Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj
**A probabilistic timing approach to hot-carrier effect estimation.**[Citation Graph (0, 0)][DBLP] ICCAD, 1992, pp:210-213 [Conf] - Terry Lee, Ibrahim N. Hajj
**A Switch-Level Matrix Approach to Transistor-Level Fault Simulation.**[Citation Graph (0, 0)][DBLP] ICCAD, 1991, pp:554-557 [Conf] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Achievable bounds on signal transition activity.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:126-129 [Conf] - Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George D. Stamoulis
**Energy and Performance Improvements in Microprocessor Design Using a Loop Cache.**[Citation Graph (0, 0)][DBLP] ICCD, 1999, pp:378-383 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
**Current-Mode Threshold Logic Gates.**[Citation Graph (0, 0)][DBLP] ICCD, 2000, pp:235-240 [Conf] - Ping-Chung Li, Ibrahim N. Hajj
**Computer-Aided Redesign of VLSI Circuits for Hot-Carrier Reliability.**[Citation Graph (0, 0)][DBLP] ICCD, 1993, pp:534-537 [Conf] - Weitong Chuang, Ibrahim N. Hajj
**Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:1503-1506 [Conf] - Pi-Yu Chung, Ibrahim N. Hajj, Janak H. Patel
**Efficient Variable Ordering Heuristics for Shared ROBDD.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:1690-1693 [Conf] - Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
**Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits.**[Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:435-438 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
**Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2001, pp:195-198 [Conf] - Andreas G. Veneris, Ibrahim N. Hajj
**Correcting multiple design errors in digital VLSI circuits.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 1999, pp:31-34 [Conf] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Low-power distributed arithmetic architectures using nonuniform memory partitioning.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 1999, pp:470-473 [Conf] - Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos
**An analytical, transistor-level energy model for SRAM-based caches.**[Citation Graph (0, 0)][DBLP] ISCAS (6), 1999, pp:198-201 [Conf] - Ninglong Lu, Ibrahim N. Hajj
**A reduced-order scheme for coupled lumped-distributed interconnect simulation.**[Citation Graph (0, 0)][DBLP] ISCAS (6), 1999, pp:250-253 [Conf] - Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos
**Using dynamic cache management techniques to reduce energy in a high-performance processor.**[Citation Graph (0, 0)][DBLP] ISLPED, 1999, pp:64-69 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
**Maximum voltage variation in the power distribution network of VLSI circuits with RLC models.**[Citation Graph (0, 0)][DBLP] ISLPED, 2001, pp:376-381 [Conf] - Ibrahim N. Hajj, George D. Stamoulis, Nikolaos Bellas, Constantine D. Polychronopoulos
**Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors.**[Citation Graph (0, 0)][DBLP] ISLPED, 1998, pp:70-75 [Conf] - Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
**An optimization technique for dual-output domino logic.**[Citation Graph (0, 0)][DBLP] ISLPED, 1999, pp:258-260 [Conf] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Decorrelating (DECOR) transformations for low-power adaptive filters.**[Citation Graph (0, 0)][DBLP] ISLPED, 1998, pp:250-255 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj
**Estimation of maximum current envelope for power bus analysis and design.**[Citation Graph (0, 0)][DBLP] ISPD, 1998, pp:141-146 [Conf] - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
**Power Bus Maximum Voltage Drop in Digital VLSI Circuits.**[Citation Graph (0, 0)][DBLP] ISQED, 2000, pp:263-268 [Conf] - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
**RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits.**[Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:205-210 [Conf] - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
**RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits.**[Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:257-0 [Conf] - Geng Bai, Ibrahim N. Hajj
**Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network.**[Citation Graph (0, 0)][DBLP] ISQED, 2002, pp:163-168 [Conf] - Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
**Post-Route Gate Sizing for Crosstalk Noise Reduction.**[Citation Graph (0, 0)][DBLP] ISQED, 2003, pp:171-176 [Conf] - Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj
**A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.**[Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:158-0 [Conf] - Murat R. Becer, Ibrahim N. Hajj
**An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling.**[Citation Graph (0, 0)][DBLP] ISQED, 2000, pp:51-58 [Conf] - Murat R. Becer, Rajendran Panda, David Blaauw, Ibrahim N. Hajj
**Pre-route Noise Estimation in Deep Submicron Integrated Circuits.**[Citation Graph (0, 0)][DBLP] ISQED, 2002, pp:413-418 [Conf] - Ninglong Lu, Ibrahim N. Hajj
**A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model.**[Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:133-138 [Conf] - Pi-Yu Chung, Ibrahim N. Hajj
**ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits.**[Citation Graph (0, 0)][DBLP] ITC, 1992, pp:742-751 [Conf] - Murat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda
**Early probabilistic noise estimation for capacitively coupled interconnects.**[Citation Graph (0, 0)][DBLP] SLIP, 2002, pp:77-83 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag
**Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1999, pp:358-0 [Conf] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1998, pp:18-23 [Conf] - Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel
**Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.**[Citation Graph (0, 0)][DBLP] VTS, 1996, pp:456-462 [Conf] - Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs
**Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits.**[Citation Graph (0, 0)][DBLP] VTS, 1999, pp:58-63 [Conf] - Ibrahim N. Hajj, Stig Skelboe
**A multilevel parallel solver for block tridiagonal and banded linear systems.**[Citation Graph (0, 0)][DBLP] Parallel Computing, 1990, v:15, n:1-3, pp:21-45 [Journal] - Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
**Postroute gate sizing for crosstalk noise reduction.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1670-1677 [Journal] - Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
**Early probabilistic noise estimation for capacitively coupled interconnects.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:337-345 [Journal] - Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
**Timing and area optimization for standard-cell VLSI circuit design.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:308-320 [Journal] - Ibrahim N. Hajj, Daniel G. Saab
**Switch-Level Logic Simulation of Digital Bipolar Circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:2, pp:251-258 [Journal] - Ping-Chung Li, Ibrahim N. Hajj
**Computer-aided redesign of VLSI circuits for hot-carrier reliability.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:453-464 [Journal] - Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
**Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:998-1012 [Journal] - Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs
**Circuit-level dictionaries of CMOS bridging faults.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:596-603 [Journal] - Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj
**A probabilistic timing approach to hot-carrier effect estimation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1223-1234 [Journal] - Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj
**Probabilistic simulation for reliability analysis of CMOS VLSI circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:439-450 [Journal] - Farid N. Najm, Ibrahim N. Hajj
**The complexity of fault detection in MOS VLSI circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:995-1001 [Journal] - Farid N. Najm, Ibrahim N. Hajj, Ping Yang
**An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1372-1381 [Journal] - Min-You Wu, Ibrahim N. Hajj
**Switching network logic approach to sequential MOS circuit design.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:782-794 [Journal] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Analytical estimation of signal transition activity from word-level statistics.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:718-733 [Journal] - Andreas G. Veneris, Ibrahim N. Hajj
**Design error diagnosis and correction via test vector simulation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1803-1816 [Journal] - Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj
**Switch-level timing simulation of bipolar ECL circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:4, pp:516-530 [Journal] - Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
**Estimation of state line statistics in sequential circuits.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:3, pp:455-473 [Journal] - Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj
**Logic design error diagnosis and correction.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:320-332 [Journal] - Pi-Yu Chung, Ibrahim N. Hajj
**Diagnosis and correction of multiple logic design errors in digital circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:233-237 [Journal] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Information-theoretic bounds on average signal transition activity [VLSI systems].**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:359-368 [Journal] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**A coding framework for low-power address and data busses.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:212-221 [Journal] - Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos
**Using dynamic cache management techniques to reduce energy in general purpose processors.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:693-708 [Journal] - Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, G. Stamoulis
**Architectural and compiler techniques for energy reduction in high-performance microprocessors.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:317-326 [Journal] - Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
**A technique for Improving dual-output domino logic.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:508-511 [Journal] **Monte-Carlo approach for power estimation in sequential circuits.**[Citation Graph (, )][DBLP]
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