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Masud H. Chowdhury: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
    Realizable RLCK circuit crunching. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:226-231 [Conf]
  2. Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail
    Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:770-779 [Conf]
  3. Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
    Realizable reduction of RLC circuits using node elimination. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:494-497 [Conf]
  4. Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
    Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:197-200 [Conf]
  5. Masud H. Chowdhury, Yehea I. Ismail
    Analysis of Coupling Noise in Dynamic Circuit. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:320-325 [Conf]
  6. Masud H. Chowdhury, Yehea I. Ismail
    Possible Noise Failure Modes in Static and Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:123-126 [Conf]
  7. Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail
    Realizable reduction of interconnect circuits including self and mutual inductances. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:271-277 [Journal]
  8. Masud H. Chowdhury, Yehea I. Ismail
    Realistic scalability of noise in dynamic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:637-641 [Journal]
  9. Abinash Roy, Noha Mahmoud, Masud H. Chowdhury
    Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:184-187 [Conf]
  10. Jingye Xu, Abinash Roy, Masud H. Chowdhury
    Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1218-1223 [Conf]
  11. Abinash Roy, Noha Mahmoud, Masud H. Chowdhury
    Delay and Clock Skew Variation due to Coupling Capacitance and Inductance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:621-624 [Conf]
  12. Abinash Roy, Masud H. Chowdhury
    Global Interconnect Optimization in the Presence of On-chip Inductance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:885-888 [Conf]
  13. Jingye Xu, Abinash Roy, Masud H. Chowdhury
    Power Consumption Analysis of Flip-flop Based Interconnect Pipelining. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3716-3719 [Conf]
  14. Vivek Nigam, Masud H. Chowdhury, Roland Priemer
    Compound noise analysis in digital circuits using blind source separation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  15. Fast bus waveform estimation at the presence of coupling noise. [Citation Graph (, )][DBLP]


  16. Improved ber performance in intra-chip rf/wireless interconnect systems. [Citation Graph (, )][DBLP]


  17. Innovative power gating for leakage reduction. [Citation Graph (, )][DBLP]


  18. Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects. [Citation Graph (, )][DBLP]


  19. Optimization technique for flip-flop inserted global interconnect. [Citation Graph (, )][DBLP]


  20. Full waveform accuracy to estimate delay in coupled digital circuits. [Citation Graph (, )][DBLP]


  21. Time diversity approach for intra-chip RF/wireless interconnect systems. [Citation Graph (, )][DBLP]


  22. Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip. [Citation Graph (, )][DBLP]


  23. Separation of Individual Noise Sources from Compound Noise Measurements in Digital Circuits. [Citation Graph (, )][DBLP]


  24. Compact thermal network model: Realization and reduction. [Citation Graph (, )][DBLP]


  25. BER performance comparison between CDMA and UWB for RF/wireless interconnect application. [Citation Graph (, )][DBLP]


  26. VSIB: A Sensor Bus Architecture for Smart-Sensor Network. [Citation Graph (, )][DBLP]


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