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Florentin Dartu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
    Piece-wise approximations of RLCK circuit responses using moment matching. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:927-932 [Conf]
  2. Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail
    Statistical static timing analysis: how simple can we get? [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:652-657 [Conf]
  3. Aseem Agarwal, Florentin Dartu, David Blaauw
    Statistical gate delay model considering multiple input switching. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:658-663 [Conf]
  4. Seung Hoon Choi, Kaushik Roy, Florentin Dartu
    Timed pattern generation for noise-on-delay calculation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:870-873 [Conf]
  5. Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage
    A Gate-Delay Model for high-Speed CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:576-580 [Conf]
  6. Florentin Dartu, Lawrence T. Pileggi
    Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:46-51 [Conf]
  7. Florentin Dartu, Lawrence T. Pileggi
    TETA: Transistor-Level Engine for Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:595-598 [Conf]
  8. Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi
    RC-Interconnect Macromodels for Timing Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:544-547 [Conf]
  9. Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi
    An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:611-616 [Conf]
  10. Florentin Dartu, Anirudh Devgan, Noel Menezes
    Variability modeling and variability-aware design in deep submicron integrated circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:1- [Conf]
  11. Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
    Weibull Based Analytical Waveform Model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:161-168 [Conf]
  12. Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
    Modeling unbuffered latches for timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:254-260 [Conf]
  13. Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage
    RC interconnect synthesis-a moment fitting approach. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:418-425 [Conf]
  14. Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
    Expanding the frequency range of AWE via time shifting. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:935-938 [Conf]
  15. Kenneth S. Stevens, Florentin Dartu
    Algorithms for MIS vector generation and pruning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:408-414 [Conf]
  16. Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi
    CMOS Gate Delay Models for General RLC Loading. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:224-229 [Conf]
  17. Ion Constatin Tesu, Florentin Dartu
    Piecewise Linear Macromodels for Elementary Logic and Fuzzy Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1718-1721 [Conf]
  18. Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail
    Weibull-based analytical waveform model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1156-1168 [Journal]
  19. Emrah Acar, Florentin Dartu, Lawrence T. Pileggi
    TETA: transistor-level waveform evaluation for timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:605-616 [Journal]
  20. Florentin Dartu, Noel Menezes, Lawrence T. Pileggi
    Performance computation for precharacterized CMOS gates with RC loads. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:544-553 [Journal]

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