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Afshin Abdollahi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
    An effective power mode transition technique in MTCMOS circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:37-42 [Conf]
  2. Afshin Abdollahi, Massoud Pedram
    A new canonical form for fast boolean matching in logic synthesis and verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:379-384 [Conf]
  3. Afshin Abdollahi, Massoud Pedram
    Analysis and synthesis of quantum circuits by using quantum decision diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:317-322 [Conf]
  4. Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh
    Precomputation-based Guarding for Dynamic and Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:90-97 [Conf]
  5. Afshin Abdollahi, Massoud Pedram, Farzan Fallah
    Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1, 2. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:213-218 [Conf]
  6. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
    Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:49-54 [Conf]
  7. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
    Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:77-82 [Conf]
  8. Afshin Abdollahi, Farzan Fallah
    Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:419-424 [Conf]
  9. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
    Leakage current reduction in CMOS VLSI circuits by input vector control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:140-154 [Journal]
  10. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
    A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:80-89 [Journal]

  11. Signature based Boolean matching in the presence of don't cares. [Citation Graph (, )][DBLP]


  12. Cost aware fault tolerant logic synthesis in presence of soft errors. [Citation Graph (, )][DBLP]


  13. Probabilistic decision diagrams for exact probabilistic analysis. [Citation Graph (, )][DBLP]


  14. Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit. [Citation Graph (, )][DBLP]


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