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Chandramouli V. Kashyap: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout
    A multi-port current source model for multiple-input switching effects in CMOS library cells. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:247-252 [Conf]
  2. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
    Delay and slew metrics using the lognormal distribution. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:382-385 [Conf]
  3. Chandramouli V. Kashyap, Byron Krauter
    A realizable driving point model for on-chip interconnect with inductance. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:190-195 [Conf]
  4. Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter
    A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:186-189 [Conf]
  5. Anirudh Devgan, Chandramouli V. Kashyap
    Block-based Static Timing Analysis with Uncertainty. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:607-614 [Conf]
  6. Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan
    An "Effective" Capacitance Based Delay Metric for RC Interconnect. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:229-234 [Conf]
  7. Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
    A delay metric for RC circuits based on the Weibull distribution. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:620-624 [Conf]
  8. Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
    Realizable reduction of RLC circuits using node elimination. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:494-497 [Conf]
  9. Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter
    Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:197-200 [Conf]
  10. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:104-109 [Conf]
  11. Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
    A two moment RC delay metric for performance optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:69-74 [Conf]
  12. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    Closed form expressions for extending step delay and slew metrics to ramp inputs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:24-31 [Conf]
  13. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    PERI: a technique for extending delay and slew metrics to ramp inputs. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:57-62 [Conf]
  14. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:136-141 [Journal]
  15. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
    Closed-form delay and slew metrics made easy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1661-1669 [Journal]
  16. Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
    RC delay metrics for performance optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:571-582 [Journal]
  17. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:509-516 [Journal]
  18. Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
    A delay metric for RC circuits based on the Weibull distribution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:443-447 [Journal]
  19. Kip Killpack, Chandramouli V. Kashyap, Eli Chiprout
    Silicon Speedpath Measurement and Feedback into EDA flows. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:390-395 [Conf]
  20. Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap
    Fast Interconnect and Gate Timing Analysis for Performance Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1383-1388 [Journal]

  21. Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. [Citation Graph (, )][DBLP]


  22. A "true" electrical cell model for timing, noise, and power grid verification. [Citation Graph (, )][DBLP]


  23. A framework for block-based timing sensitivity analysis. [Citation Graph (, )][DBLP]


  24. A nonlinear cell macromodel for digital applications. [Citation Graph (, )][DBLP]


  25. Silicon feedback to improve frequency of high-performance microprocessors: an overview. [Citation Graph (, )][DBLP]


  26. Quantifying robustness metrics in parameterized static timing analysis. [Citation Graph (, )][DBLP]


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