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Publications of Author

1. Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout
   A multi-port current source model for multiple-input switching effects in CMOS library cells. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:247-252 [Conf]
   
2. Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail
   Statistical static timing analysis: how simple can we get? [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:652-657 [Conf]
   
3. Chung-Ping Chen, Noel Menezes
   Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:502-506 [Conf]
   
4. Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage
   A Gate-Delay Model for high-Speed CMOS Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1994, pp:576-580 [Conf]
   
5. Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi
   Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. [Citation Graph (0, 0)][DBLP]
   DAC, 1995, pp:690-695 [Conf]
   
6. Farid N. Najm, Noel Menezes
   Statistical timing analysis based on a timing yield model. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:460-465 [Conf]
   
7. Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage
   Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. [Citation Graph (0, 0)][DBLP]
   DAC, 1993, pp:165-170 [Conf]
   
8. Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer
   Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. [Citation Graph (0, 0)][DBLP]
   EDAC-ETC-EUROASIC, 1994, pp:332-337 [Conf]
   
9. Florentin Dartu, Anirudh Devgan, Noel Menezes
   Variability modeling and variability-aware design in deep submicron integrated circuits. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2005, pp:1- [Conf]
   
10. Noel Menezes, Ross Baldick, Lawrence T. Pileggi
    A sequential quadratic programming approach to concurrent gate and wire sizing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:144-151 [Conf]
    
11. Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage
    RC interconnect synthesis-a moment fitting approach. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:418-425 [Conf]
    
12. Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi
    Clustering and Load Balancing for Buffered Clock Tree Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:217-223 [Conf]
    
13. Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
    The scaling challenge: can correct-by-construction design help? [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:51-58 [Conf]
    
14. Noel Menezes, Chung-Ping Chen
    Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:476-0 [Conf]
    
15. Noel Menezes, Sachin S. Sapatnekar
    Optimization and Analysis Techniques for the Deep Submicron Regime. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:3-4 [Conf]
    
16. Florentin Dartu, Noel Menezes, Lawrence T. Pileggi
    Performance computation for precharacterized CMOS gates with RC loads. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:544-553 [Journal]
    
17. Noel Menezes, Ross Baldick, Lawrence T. Pileggi
    A sequential quadratic programming approach to concurrent gate and wire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:867-881 [Journal]
    
18. Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi
    Post-processing of clock trees via wiresizing and buffering for robust design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:691-701 [Journal]
    
19. Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi
    Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:2, pp:210-215 [Journal]
    
20. Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
    Repeater scaling and its impact on CAD. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:451-463 [Journal]
    
21. Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James Tschanz, Vivek De
    Comparative Analysis of Conventional and Statistical Design Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:238-243 [Conf]
    
22. Noel Menezes
    The good, the bad, and the statistical. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:168- [Conf]
    
23. 
    A "true" electrical cell model for timing, noise, and power grid verification. [Citation Graph (, )][DBLP]
    
    
24. 
    A nonlinear cell macromodel for digital applications. [Citation Graph (, )][DBLP]