The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Gabriele Saucier: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pierre Abouzeid, K. Sakouti, Gabriele Saucier, F. Poirot
    Multilevel Synthesis Minimizing the Routing Factor. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:365-368 [Conf]
  2. M. Crastes, K. Sakouti, Gabriele Saucier
    A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:93-98 [Conf]
  3. Kella Knack, Gordan Hyland, Jim Jasmin, John Frediani, Tom Reiner, Steven Trimberger, Gabriele Saucier
    Design Automation Tools for FPGA Design (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:676- [Conf]
  4. E. F. M. Kouka, Gabriele Saucier
    An Application of Exploratory Data Analysis Techniques to Floorplan Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:654-658 [Conf]
  5. Helena Krupnova, Ali Abbara, Gabriele Saucier
    A Hierarchy-Driven FPGA Partitioning Method. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:522-525 [Conf]
  6. Gabriele Saucier, C. Duff, F. Poirot
    State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:321-326 [Conf]
  7. Gabriele Saucier, Ghislaine Thuau
    Systematic and optimized layout of MOS cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:53-61 [Conf]
  8. Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier
    Who Owns the Platform? [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:238-239 [Conf]
  9. L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, Gabriele Saucier
    E-Design Based on the Reuse Paradigm. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:214-220 [Conf]
  10. Helena Krupnova, Gabriele Saucier
    Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:587-0 [Conf]
  11. Régis Leveugle, R. Rochet, Gabriele Saucier
    Alternative Approaches to Fault Detection in FSMs. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:271-279 [Conf]
  12. R. Rochet, Régis Leveugle, Gabriele Saucier
    Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:9-16 [Conf]
  13. T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier
    Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:14-18 [Conf]
  14. Daniel R. Brasen, Gabriele Saucier
    FPGA Partitioning for Critical Paths. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:99-103 [Conf]
  15. C. Safinia, Régis Leveugle, Gabriele Saucier
    Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:349-353 [Conf]
  16. D. Jacquet, Gabriele Saucier
    Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:256-260 [Conf]
  17. E. Dupont, Jeanne Idt, Gabriele Saucier
    A Rule-Based System for the Optimal State Assignment of Controllers. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:915-923 [Conf]
  18. Helena Krupnova, B. Behnam, Gabriele Saucier
    Block and IP Wrapping for Efficient Design on FPGAs (Abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:256- [Conf]
  19. Helena Krupnova, Christian Rabedaoro, Gabriele Saucier
    Synthesis and Floorplanning for Large Hierarchical FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:105-111 [Conf]
  20. Helena Krupnova, Gabriele Saucier
    Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:251- [Conf]
  21. S. A. Senouci, A. Amoura, Helena Krupnova, Gabriele Saucier
    Timing Driven Floorplanning on Programmable Hierarchical Targets. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:85-92 [Conf]
  22. Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier
    A Knowledge-Based System for Prototyping on FPFAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:89-98 [Conf]
  23. Helena Krupnova, Gabriele Saucier
    FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:68-77 [Conf]
  24. Helena Krupnova, Gabriele Saucier
    Hierarchical Interactive Approach to Partition Large Designs into FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:101-110 [Conf]
  25. Bernard Laurent, G. Bosco, Gabriele Saucier
    Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:462-471 [Conf]
  26. Régis Leveugle, R. Rochet, Gabriele Saucier, L. Martinez, C. Pitot
    A Synthesis Tool for Fault-Tolerant Finite State Machines. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:502-511 [Conf]
  27. T. Michel, Régis Leveugle, Gabriele Saucier
    A New Approach to Control Flow Checking Without Program Modification. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:334-343 [Conf]
  28. Manfred Glesner, M. Huch, Peter A. Ivey, T. Midwinter, Gabriele Saucier, Jacques Trilhe
    Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 1988, pp:75-91 [Conf]
  29. C. Duff, Gabriele Saucier
    State Assignment Based on the Reduced Dependency Theory and Recent Experimental Results. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:222-225 [Conf]
  30. Gabriele Saucier, Daniel R. Brasen, J. P. Hiol
    Partitioning with cone structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:236-239 [Conf]
  31. T. Besson, H. Bouzouzou, M. Crastes, I. Floricica, Gabriele Saucier
    Synthesis on Multiplexer-Based F.P.G.A. Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:163-167 [Conf]
  32. Régis Leveugle, X. Delord, Gabriele Saucier
    Influence of Error Correlations on the Signature Analysis Aliasing. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:584-587 [Conf]
  33. Pierre Abouzeid, Régis Leveugle, Gabriele Saucier
    Logic Synthesis for Automatic Layout. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:335-343 [Conf]
  34. H. Belhadj, L. Gerbaux, Marie-Claude Bertrand, Gabriele Saucier
    Specification and Synthesis of Communicating Finite State Machines. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:91-102 [Conf]
  35. L. Gerbaux, Régis Leveugle, Gabriele Saucier
    Synthesis of large controllers using ROM or PLA generators. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:47-59 [Conf]
  36. Anne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier
    ASYL: A Control Driven RTL Synthesis System using Library Blocks. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:275-291 [Conf]
  37. M. Moalla, Gabriele Saucier, Joseph Sifakis, M. Zachariades
    A Design Tool for the Multilevel Description and Simulation of Systems of Interconnected Modules. [Citation Graph (0, 0)][DBLP]
    ISCA, 1976, pp:20-27 [Conf]
  38. Catherine Bellon, Gabriele Saucier
    CADOC : A System for Computer Aided Functional Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:680-689 [Conf]
  39. X. Delord, Gabriele Saucier
    Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:936-945 [Conf]
  40. M. Karam, Régis Leveugle, Gabriele Saucier
    Hierarchical Test Generation Based on Delayed Propagation. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:739-747 [Conf]
  41. Régis Leveugle, Gabriele Saucier
    Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:355-363 [Conf]
  42. Michel Crastes de Paulet, M. Karam, Gabriele Saucier
    Testability Expertise and Test Planning from High-Level Specifications. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:692-699 [Conf]
  43. Helena Krupnova, Christian Rabedaoro, Gabriele Saucier
    FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:128-133 [Conf]
  44. Helena Krupnova, Gabriele Saucier
    FPGA Technology Snapshot: Current Devices and Design Tools. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:200-0 [Conf]
  45. Helena Krupnova, D. D. A. Vu, Gabriele Saucier, M. Boubal
    Real Time Prototyping Method and a Case Study. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:13-18 [Conf]
  46. D. Jacquet, Gabriele Saucier
    Design of a dedicated neural network on silicon: application to optical character recognition. [Citation Graph (0, 0)][DBLP]
    VLSI, 1993, pp:169-178 [Conf]
  47. J. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, L. Masse-Navette
    A Customizable Neural Processor for Distributed Neural Network. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:167-176 [Conf]
  48. Bernard Laurent, G. Bosco, Gabriele Saucier
    Fast Arithmetic on Xilinx 5200 FPGA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:322-325 [Conf]
  49. Ahmed Boubekeur, Jean-Luc Patry, Gabriele Saucier, Jacques Trilhe
    Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:4, pp:29-39 [Journal]
  50. Robert Cuykendall, Antun Domic, William H. Joyner, Steve C. Johnson, Steven H. Kelem, Dennis McBride, Jack Mostow, John E. Savage, Gabriele Saucier
    Design synthesis in VLSI and software engineering. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 1984, v:4, n:1, pp:7-12 [Journal]
  51. Catherine Bellon, Gabriele Saucier
    Protection Against External Errors in a Dedicated System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:4, pp:311-317 [Journal]
  52. Régis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn
    The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:12, pp:1398-1406 [Journal]
  53. Régis Leveugle, Gabriele Saucier
    Optimized Synthesis of Concurrently Checked Controllers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:419-425 [Journal]
  54. Chantal Robach, Gabriele Saucier
    Diversified Test Methods for Local Control Units. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:5, pp:562-567 [Journal]
  55. Chantal Robach, Gabriele Saucier
    Dynamic Testing of Control Units. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:7, pp:617-623 [Journal]
  56. Chantal Robach, Gabriele Saucier, J. Lebrun
    Processor Testability and Design Consequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:6, pp:645-652 [Journal]
  57. Ghislaine Thuau, Gabriele Saucier
    Optimized Layout of MOS Cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:1, pp:79-87 [Journal]
  58. Pierre Abouzeid, Belgacem Babba, Michel Crastes de Paulet, Gabriele Saucier
    Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:913-925 [Journal]
  59. Daniel R. Brasen, Gabriele Saucier
    Using cone structures for circuit partitioning into FPGA packages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:592-600 [Journal]
  60. Gabriele Saucier, Pierre Abouzeid
    Lexicographical expressions of Boolean functions with application to multilevel synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1642-1654 [Journal]
  61. Gabriele Saucier, Michel Crastes de Paulet, P. Sicard
    ASYL: A Rule-Based System for Controller Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1088-1097 [Journal]

  62. State assignment of controllers for optimal area implementation. [Citation Graph (, )][DBLP]


  63. Multi-level synthesis on PALs. [Citation Graph (, )][DBLP]


Search in 0.006secs, Finished in 0.008secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002