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Manuel A. d'Abreu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther
    Microprocessor Testing: Which Technique is Best? (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:294- [Conf]
  2. E. Berkcan, Manuel A. d'Abreu, W. Laughton
    Analog Compilation Based on Successive Decompositions. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:369-375 [Conf]
  3. M. Dragomirecky, Ephraim P. Glinert, Jeffrey R. Jasica, David A. Duff, William D. Smith, Manuel A. d'Abreu
    High-Level Graphical User Interface Management in the FACE Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:549-554 [Conf]
  4. William D. Smith, David A. Duff, M. Dragomirecky, J. Caldwell, Michael J. Hartman, Jeffrey R. Jasica, Manuel A. d'Abreu
    FACE Core Environment: The Model and Its Application in CAE/CAD Tool Development. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:466-471 [Conf]
  5. Manuel A. d'Abreu
    Noise-Its Sources, and Impact on Design and Test of Mixed Signal Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:370-376 [Conf]
  6. Abhijit Chatterjee, Manuel A. d'Abreu
    Concurrent Error Detection and Fault-Tolerance in Linear Digital State Variable Systems. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:136-143 [Conf]
  7. Prakash Arunachalam, Jacob A. Abraham, Manuel A. d'Abreu
    A Hierarchal Approach for Power Reduction in VLSI Chips. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:182-0 [Conf]
  8. Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu
    Automatic test generation for linear digital systems with bi-level search using matrix transform methods. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:224-228 [Conf]
  9. Abhijit Chatterjee, Manuel A. d'Abreu
    Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:212-215 [Conf]
  10. Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu
    Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1118-1127 [Conf]
  11. Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. Abraham
    Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:160-166 [Conf]
  12. Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu
    Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:154-159 [Conf]
  13. Rathish Jayabharathi, Manuel A. d'Abreu, Jacob A. Abraham
    FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:232-235 [Conf]
  14. Manuel A. d'Abreu
    Manufacturing and Test Considerations in System-On-Chip Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:176-177 [Conf]
  15. Abhijit Chatterjee, Manuel A. d'Abreu
    The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:7, pp:794-808 [Journal]
  16. Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu
    Greedy hardware optimization for linear digital circuits using number splitting and refactorization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:423-431 [Journal]

  17. Impact of SoC power management techniques on verification and testing. [Citation Graph (, )][DBLP]

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