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Miron Abramovici: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller
    A reconfigurable design-for-debug infrastructure for SoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:7-12 [Conf]
  2. Miron Abramovici, Krishna B. Rajan, David T. Miller
    Freeze!: A New Approach for Testing Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:22-25 [Conf]
  3. Miron Abramovici, Charles E. Stroud, Marty Emmert
    Using embedded FPGAs for SoC yield improvement. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:713-724 [Conf]
  4. Miron Abramovici, José T. de Sousa, Daniel G. Saab
    A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:684-690 [Conf]
  5. Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick
    Low-cost sequential ATPG with clock-control DFT. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:243-248 [Conf]
  6. Mahesh A. Iyer, David E. Long, Miron Abramovici
    Identifying Sequential Redundancies Without Search. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:457-462 [Conf]
  7. Prashant S. Parikh, Miron Abramovici
    A Cost-Based Approach to Partial Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:255-259 [Conf]
  8. Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici
    FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:747-0 [Conf]
  9. John M. Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici
    On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:445-454 [Conf]
  10. Miron Abramovici, John M. Emmert, Charles E. Stroud
    Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2001, pp:73-92 [Conf]
  11. Miron Abramovici, Premachandran R. Menon
    Fault simulation on reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:182-191 [Conf]
  12. Miron Abramovici, José T. de Sousa
    A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:306-307 [Conf]
  13. John M. Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici
    Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:165-174 [Conf]
  14. Charles E. Stroud, Ping Chen, Srinivasa Konala, Miron Abramovici
    Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:107-113 [Conf]
  15. Miron Abramovici, Daniel G. Saab
    Satisfiability on reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:448-456 [Conf]
  16. John M. Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici
    Performance Penalty for Fault Tolerance in Roving STARs. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:545-554 [Conf]
  17. Miron Abramovici, Charles E. Stroud
    BIST-Based Delay-Fault Testing in FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:131-134 [Conf]
  18. Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John M. Emmert
    On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:27-33 [Conf]
  19. Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John M. Emmert
    Improving On-Line BIST-Based Diagnosis for Roving STARs. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:31-39 [Conf]
  20. Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon
    A logic simulation machine. [Citation Graph (0, 0)][DBLP]
    ISCA, 1982, pp:148-157 [Conf]
  21. Miron Abramovici
    Low-Cost Fault Simulation: Why, When and How. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:795- [Conf]
  22. Miron Abramovici
    DOs and DON'Ts in Computing Fault Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:594- [Conf]
  23. Miron Abramovici, Mahesh A. Iyer
    One-Pass Redundancy Identification and Removal. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:807-815 [Conf]
  24. Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller
    Test Generation In Lamp2: System Overview. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:45-48 [Conf]
  25. Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller
    Test Generation In Lamp2: Concepts and Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:49-56 [Conf]
  26. Miron Abramovici, B. Krishnamurthy, A. Mathews, B. Rogers, M. Schulz, S. Seth, John A. Waicukauski
    What is the Path to Fast Fault Simulation? [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:183-192 [Conf]
  27. Miron Abramovici, James J. Kulikowski, Rabindra K. Roy
    The Best Flip-Flops to Scan. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:166-173 [Conf]
  28. Miron Abramovici, Premachandran R. Menon
    A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:138-142 [Conf]
  29. Miron Abramovici, Prashant S. Parikh
    Warning: 100% Fault Coverage May Be Misleading!! [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:662-668 [Conf]
  30. Miron Abramovici, Prashant S. Parikh, Ben Mathew, Daniel G. Saab
    On Selecting Flip-Flops for Partial Reset. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:1008-1012 [Conf]
  31. Miron Abramovici, Charles E. Stroud
    DIST-based detection and diagnosis of multiple faults in FPGAs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:785-794 [Conf]
  32. Miron Abramovici, Charles E. Stroud, Carter Hamilton, Sajitha Wijesuriya, Vinay Verma
    Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:973-982 [Conf]
  33. Mahesh A. Iyer, Miron Abramovici
    Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!"). [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:259-266 [Conf]
  34. Prashant S. Parikh, Miron Abramovici
    On Combining Design for Testability Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:423-429 [Conf]
  35. Qiang Peng, Miron Abramovici, Jacob Savir
    MUST: multiple-stem analysis for identifying sequentially untestable faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:839-846 [Conf]
  36. Jongshin Shin, Xiaoming Yu, Elizabeth M. Rudnick, Miron Abramovici
    At-speed logic BIST using a frozen clock testing strategy. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:64-71 [Conf]
  37. Charles E. Stroud, Eric Lee, Miron Abramovici
    BIST-Based Diagnostics of FPGA Logic Blocks. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:539-547 [Conf]
  38. Charles E. Stroud, Eric Lee, Srinivasa Konala, Miron Abramovici
    Using ILA Testing for BIST in FPGAs. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:68-75 [Conf]
  39. Charles E. Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici
    BIST-Based Diagnosis of FPGA Interconnect. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:618-627 [Conf]
  40. Charles E. Stroud, Sajitha Wijesuriya, Carter Hamilton, Miron Abramovici
    Built-in self-test of FPGA interconnect. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:404-411 [Conf]
  41. Mahesh A. Iyer, Miron Abramovici
    Low-Cost Redundancy Identification for Combinatorial Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:315-318 [Conf]
  42. David E. Long, Mahesh A. Iyer, Miron Abramovici
    Identifying sequentially untestable faults using illegal states. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:4-11 [Conf]
  43. Krishna B. Rajan, David E. Long, Miron Abramovici
    Increasing testability by clock transformation (getting rid of those darn states). [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:224-230 [Conf]
  44. Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici
    Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:387-392 [Conf]
  45. Miron Abramovici, José T. de Sousa
    A SAT Solver Using Reconfigurable Hardware and Virtual Logic. [Citation Graph (0, 0)][DBLP]
    J. Autom. Reasoning, 2000, v:24, n:1/2, pp:5-36 [Journal]
  46. Elizabeth M. Rudnick, Miron Abramovici
    Compact Test Generation Using a Frozen Clock Testing Strategy. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2000, v:16, n:5, pp:703-717 [Journal]
  47. Miron Abramovici
    A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:7, pp:672-677 [Journal]
  48. Miron Abramovici, Melvin A. Breuer
    On Redundancy and Fault Detection in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:11, pp:864-865 [Journal]
  49. Miron Abramovici, Melvin A. Breuer
    Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:6, pp:451-460 [Journal]
  50. Miron Abramovici, Melvin A. Breuer
    Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:12, pp:1165-1172 [Journal]
  51. Miron Abramovici, Premachandran R. Menon
    A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:7, pp:658-663 [Journal]
  52. Miron Abramovici, Premachandran R. Menon, David T. Miller
    Checkpoint Faults are not Sufficient Target Faults for Test Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:8, pp:769-771 [Journal]
  53. Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon
    A Logic Simulation Machine. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:82-94 [Journal]
  54. Miron Abramovici, David T. Miller, Rabindra K. Roy
    Dynamic redundancy identification in automatic test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:3, pp:404-407 [Journal]
  55. Premachandran R. Menon, Ytzhak H. Levendel, Miron Abramovici
    SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:6, pp:738-747 [Journal]
  56. Xiaoming Yu, Miron Abramovici
    Sequential circuit ATPG using combinational algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1294-1310 [Journal]
  57. David E. Long, Mahesh A. Iyer, Miron Abramovici
    FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:631-657 [Journal]
  58. Miron Abramovici, Charles E. Stroud, John M. Emmert
    Online BIST and BIST-based diagnosis of FPGA logic blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1284-1294 [Journal]
  59. John M. Emmert, Charles E. Stroud, Miron Abramovici
    Online Fault Tolerance for FPGA Logic Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:216-226 [Journal]
  60. Mahesh A. Iyer, Miron Abramovici
    FIRE: a fault-independent combinational redundancy identification algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:295-301 [Journal]
  61. Miron Abramovici, Charles E. Stroud
    BIST-based test and diagnosis of FPGA logic blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:159-172 [Journal]

  62. You can catch more bugs with transaction level honey. [Citation Graph (, )][DBLP]


  63. Bridging pre-silicon verification and post-silicon validation. [Citation Graph (, )][DBLP]


  64. In-System Silicon Validation and Debug. [Citation Graph (, )][DBLP]


  65. We need more standards like IEEE 1500. [Citation Graph (, )][DBLP]


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