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José T. de Sousa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Miron Abramovici, José T. de Sousa, Daniel G. Saab
    A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:684-690 [Conf]
  2. José T. de Sousa, Vishwani D. Agrawal
    Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:640-644 [Conf]
  3. Ateet Bhalla, Inês Lynce, José T. de Sousa, João P. Marques Silva
    Heuristic-Based Backtracking for Propositional Satisfiability. [Citation Graph (0, 0)][DBLP]
    EPIA, 2003, pp:116-130 [Conf]
  4. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams
    Fault Modeling and Defect Level Projections in Digital ICs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:436-442 [Conf]
  5. Miron Abramovici, José T. de Sousa
    A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:306-307 [Conf]
  6. N. A. Reis, José T. de Sousa
    On Implementing a Configware/Software SAT Solver. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:282-283 [Conf]
  7. Victor Gonçalves, José T. de Sousa, Fernando M. Gonçalves
    A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:481-486 [Conf]
  8. A. Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa
    Fault Simulation Using Partially Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:839-848 [Conf]
  9. José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura
    DARP - A Digital Audio Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:556-566 [Conf]
  10. C. J. Tavares, C. Bungardean, G. M. Matos, José T. de Sousa
    Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:344-353 [Conf]
  11. José T. de Sousa
    On Defect-Level Estimation and the Clustering Effect. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:257-268 [Conf]
  12. M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Physical DFT for High Coverage of Realistic Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:642-651 [Conf]
  13. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira
    IC Defects-Based Testability Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:500-509 [Conf]
  14. Ateet Bhalla, Inês Lynce, José T. de Sousa, João P. Marques Silva
    Heuristic Backtracking Algorithms for SAT. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:69-74 [Conf]
  15. Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.
    A fast SAT solver algorithm best suited to reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:131-136 [Conf]
  16. Miron Abramovici, José T. de Sousa
    A SAT Solver Using Reconfigurable Hardware and Virtual Logic. [Citation Graph (0, 0)][DBLP]
    J. Autom. Reasoning, 2000, v:24, n:1/2, pp:5-36 [Journal]
  17. Ateet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva
    Heuristic-Based Backtracking Relaxation for Propositional Satisfiability. [Citation Graph (0, 0)][DBLP]
    J. Autom. Reasoning, 2005, v:35, n:1-3, pp:3-24 [Journal]
  18. Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
    Guest Editors' Introduction: Field Programmable Logic and Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1361-1362 [Journal]
  19. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams
    Defect level evaluation in an IC design environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1286-1293 [Journal]
  20. Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.
    A Fast SAT Solver Strategy Based on Negated Clauses. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:110-115 [Conf]

  21. Improved diagnosis of realistic interconnect shorts. [Citation Graph (, )][DBLP]


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