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Daniel G. Saab: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Miron Abramovici, José T. de Sousa, Daniel G. Saab
    A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:684-690 [Conf]
  2. David Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh
    Automatic Generation of Behavioral Models from Switch-Level Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:179-184 [Conf]
  3. Fatih Kocan, Daniel G. Saab
    Dynamic Fault Diagnosis on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:691-696 [Conf]
  4. Daniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj
    Delay Modeling and Time of Bipolar Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:288-293 [Conf]
  5. Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel
    Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:40-45 [Conf]
  6. Miron Abramovici, Daniel G. Saab
    Satisfiability on reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:448-456 [Conf]
  7. Qiang Qiang, Daniel G. Saab, Jacob A. Abraham
    An Emulation Model for Sequential ATPG-Based Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:469-474 [Conf]
  8. Daniel G. Saab, Fatih Kocan, Jacob A. Abraham
    Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1172-1176 [Conf]
  9. Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham
    Reducing verification overhead with RTL slicing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:399-404 [Conf]
  10. David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham
    SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:66-69 [Conf]
  11. Chung-Hsing Chen, Daniel G. Saab
    Behavioral synthesis for testability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:612-615 [Conf]
  12. Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab
    BETA: Behavioral Testability Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:202-205 [Conf]
  13. Gwan S. Choi, Ravishankar K. Iyer, Daniel G. Saab
    Fault behavior dictionary for simulation of device-level transients. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:6-9 [Conf]
  14. Fatih Kocan, Daniel G. Saab
    Concurrent D-algorithm on reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:152-156 [Conf]
  15. Ben Mathew, Daniel G. Saab
    Augmented partial reset. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:716-719 [Conf]
  16. Daniel G. Saab, Youssef Saab, Jacob A. Abraham
    CRIS: a test cultivation program for sequential VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:216-219 [Conf]
  17. Daniel G. Saab, Youssef Saab, Jacob A. Abraham
    Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:40-43 [Conf]
  18. Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab
    Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:463-466 [Conf]
  19. Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham
    Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:461-463 [Conf]
  20. Jalal A. Wehbeh, Daniel G. Saab
    Hierarchical Simulation of MOS Circuits Using Extracted Functional Models. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:512-515 [Conf]
  21. Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
    Database Recovery Using Redundant Disk Arrays. [Citation Graph (0, 14)][DBLP]
    ICDE, 1992, pp:176-183 [Conf]
  22. Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
    Assigning Sites fto Redundant Clusters in a Distributed Storage System. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:64-71 [Conf]
  23. Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
    Performance of Redundant Disk Array Organizations in Transaction Processing Environments. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:138-145 [Conf]
  24. Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab
    Verifying Properties Using Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:194-202 [Conf]
  25. Miron Abramovici, Prashant S. Parikh, Ben Mathew, Daniel G. Saab
    On Selecting Flip-Flops for Partial Reset. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:1008-1012 [Conf]
  26. Ben Mathew, Daniel G. Saab
    DFT & ATPG: Together Again. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:262-271 [Conf]
  27. Praveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab
    CHEETA: Composition of Hierarchical Sequential Tests Using ATKET. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:606-615 [Conf]
  28. Jalal A. Wehbeh, Daniel G. Saab
    On the Initialization of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:233-239 [Conf]
  29. Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
    Site Partitioning for Distributed Redundant Disk Arrays. [Citation Graph (0, 0)][DBLP]
    RIDE-TQP, 1992, pp:214- [Conf]
  30. Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham
    Design of a scalable parallel switch-level simulator for VLSI. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:615-624 [Conf]
  31. Qiang Qiang, Daniel G. Saab, Jacob A. Abraham
    Checking Nested Properties Using Bounded Model Checking and Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:225-230 [Conf]
  32. Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula
    Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:243-248 [Conf]
  33. Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab
    Hierarchical Test Generation for Systems On a Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:198-0 [Conf]
  34. Jacob A. Abraham, Daniel G. Saab
    Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:6- [Conf]
  35. Jalal A. Wehbeh, Daniel G. Saab
    Initialization of sequential circuits and its application to ATPG. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:246-253 [Conf]
  36. Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
    Recovery Issues in Databases Using Redundant Disk Arrays. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:17, n:1-2, pp:75-89 [Journal]
  37. Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab
    Site Partitioning for Redundant Arrays of Distributed Disks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:33, n:1, pp:1-11 [Journal]
  38. Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab
    Structural and behavioral synthesis for testability techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:777-785 [Journal]
  39. Chung-Hsing Chen, Daniel G. Saab
    A novel behavioral testability measure. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1960-1970 [Journal]
  40. Ibrahim N. Hajj, Daniel G. Saab
    Switch-Level Logic Simulation of Digital Bipolar Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:2, pp:251-258 [Journal]
  41. Ben Mathew, Daniel G. Saab
    Combining multiple DFT schemes with test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:685-696 [Journal]
  42. Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham
    VLSI logic and fault simulation on general-purpose parallel computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:446-460 [Journal]
  43. Daniel G. Saab, Youssef Saab, Jacob A. Abraham
    Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1278-1285 [Journal]
  44. Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj
    Switch-level timing simulation of bipolar ECL circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:4, pp:516-530 [Journal]
  45. Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham
    Benchmarking Parallel Processing Platforms: An Applications Perspective. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:8, pp:947-954 [Journal]
  46. Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab
    Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:173-178 [Conf]
  47. Daniel G. Saab
    Parallel-concurrent fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:356-364 [Journal]
  48. Fatih Kocan, Daniel G. Saab
    ATPG for combinational circuits on configurable hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:117-129 [Journal]
  49. Fatih Kocan, Daniel G. Saab
    Correction to "ATPG for combinational circuits on configurable hardware". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:374-374 [Journal]

  50. Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. [Citation Graph (, )][DBLP]


  51. Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times. [Citation Graph (, )][DBLP]


  52. Derivation of signal flow for switch-level simulation. [Citation Graph (, )][DBLP]


  53. Complementary nano-electromechanical switches for ultra-low power embedded processors. [Citation Graph (, )][DBLP]


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