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Publications of Author

1. King C. Ho, Sarma Sastry
   Flexible Transistor Matrix (FTM). [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:475-480 [Conf]
   
2. C. P. Ravi Kumar, Sarma Sastry
   Parallel Placement on Reduced Array Architecture. [Citation Graph (0, 0)][DBLP]
   DAC, 1988, pp:121-127 [Conf]
   
3. Yung-Te Lai, Sarma Sastry
   Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification. [Citation Graph (0, 0)][DBLP]
   DAC, 1992, pp:608-613 [Conf]
   
4. Amitava Majumdar, Sarma Sastry
   On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1992, pp:341-346 [Conf]
   
5. Sarma Sastry, Amitava Majumdar
   A Branching Process Model for Observability Analysis of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:452-457 [Conf]
   
6. Sarma Sastry, Jen-I Pi
   An Investigation into Statistical Properties of Partitioning and Floorplanning Problems. [Citation Graph (0, 0)][DBLP]
   DAC, 1989, pp:382-387 [Conf]
   
7. Yung-Te Lai, Sarma Sastry, Massoud Pedram
   Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification. [Citation Graph (0, 0)][DBLP]
   ICCD, 1992, pp:452-458 [Conf]
   
8. Viktor K. Prasanna, Sarma Sastry
   A General Purpose VLSI Array for Efficient Signal and Image Processsing. [Citation Graph (0, 0)][DBLP]
   ICPP, 1987, pp:917-920 [Conf]
   
9. C. P. Ravikumar, Sarma Sastry
   Parallel Placement on Hypercube Architecture. [Citation Graph (0, 0)][DBLP]
   ICPP (3), 1989, pp:97-101 [Conf]
   
10. Amitava Majumdar, Sarma Sastry
    Statistical Analysis of Controllability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:55-60 [Conf]
    
11. Amitava Majumdar, Sarma Sastry
    Probabilistic characterization of controllability in general homogeneous circuits. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1993, v:25, n:2, pp:76-93 [Journal]
    
12. Sarma Sastry, Melvin A. Breuer
    Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:9, pp:933-946 [Journal]
    
13. Sarma Sastry, Amitava Majumdar
    Test efficiency analysis of random self-test of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:390-398 [Journal]
    
14. Sarma Sastry, Alice C. Parker
    Stochastic Models for Wireability Analysis of Gate Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:52-65 [Journal]
    
15. Sarma Sastry, Jen-I Pi
    Estimating the minimum of partitioning and floorplanning problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:273-282 [Journal]