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Elizabeth M. Rudnick: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick
    Low-cost sequential ATPG with clock-control DFT. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:243-248 [Conf]
  2. Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel
    Non-Scan Design-for-Testability Techniques for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:236-241 [Conf]
  3. Elizabeth M. Rudnick, Janak H. Patel
    Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:183-188 [Conf]
  4. Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
    Sequential Circuit Test Generation in a Genetic Algorithm Framework. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:698-704 [Conf]
  5. Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel
    Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:133-138 [Conf]
  6. Timothy J. Bergfeld, Dirk Niggemeyer, Elizabeth M. Rudnick
    Diagnostic Testing of Embedded Memories Using BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:305-0 [Conf]
  7. Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:570-576 [Conf]
  8. Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici
    FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:747-0 [Conf]
  9. Jue Wu, Gary S. Greenstein, Elizabeth M. Rudnick
    A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:780-781 [Conf]
  10. Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel
    Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:40-45 [Conf]
  11. Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer
    A Fast and Accurate Gate-Level Transient Fault Simulation Environment. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:310-319 [Conf]
  12. Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick
    Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    GECCO, 2002, pp:1275- [Conf]
  13. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
    Effects of delay models on peak power estimation of VLSI sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:45-51 [Conf]
  14. Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel
    Enhancing high-level control-flow for improved testability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:322-328 [Conf]
  15. Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel
    Methods for Reducing Events in Sequential Circuit Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:546-549 [Conf]
  16. Elizabeth M. Rudnick, Janak H. Patel
    Simulation-based techniques for dynamic test sequence compaction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:67-73 [Conf]
  17. Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick
    A Genetic Testing Framework for Digital Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ICTAI, 2002, pp:521-526 [Conf]
  18. Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir
    Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:65-0 [Conf]
  19. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
    K2: an estimator for peak sustainable power of VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:178-183 [Conf]
  20. Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel
    Testability Insertion in Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:139-144 [Conf]
  21. Elizabeth M. Rudnick, W. Kent Fuchs, Janak H. Patel
    Diagnostic Fault Simulation of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:178-186 [Conf]
  22. Elizabeth M. Rudnick, Janak H. Patel
    Putting the Squeeze on Test Sequences. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:723-732 [Conf]
  23. Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz
    On Potential Fault Detection in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:142-149 [Conf]
  24. Jongshin Shin, Xiaoming Yu, Elizabeth M. Rudnick, Miron Abramovici
    At-speed logic BIST using a frozen clock testing strategy. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:64-71 [Conf]
  25. Xiaoming Yu, Jue Wu, Elizabeth M. Rudnick
    Diagnostic test generation for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:225-234 [Conf]
  26. Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Redeker
    Diagnostic Testing of Embedded Memories Based on Output Tracing. [Citation Graph (0, 0)][DBLP]
    MTDT, 2000, pp:113-118 [Conf]
  27. Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel
    Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. [Citation Graph (0, 0)][DBLP]
    Workshop on Parallel and Distributed Simulation, 1997, pp:30-37 [Conf]
  28. Jue Wu, Elizabeth M. Rudnick
    A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:498-505 [Conf]
  29. Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel
    Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:542-544 [Conf]
  30. Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel
    Partial Scan Selection Based on Dynamic Reachability and Observability Information. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:174-180 [Conf]
  31. Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee
    Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:475-481 [Conf]
  32. Elizabeth M. Rudnick, Janak H. Patel
    A genetic approach to test application time reduction for full scan and partial scan circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:288-293 [Conf]
  33. Elizabeth M. Rudnick, Janak H. Patel
    Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:495-503 [Conf]
  34. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
    Automatic test generation using genetically-engineered distinguishing sequences. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:216-223 [Conf]
  35. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
    Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:188-195 [Conf]
  36. Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee
    SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:274-281 [Conf]
  37. Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel
    Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:456-462 [Conf]
  38. Dirk Niggemeyer, Elizabeth M. Rudnick
    Automatic Generation of Diagnostic March Tests. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:299-305 [Conf]
  39. Jian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel
    Static logic implication with application to redundancy identification. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:288-295 [Conf]
  40. Elizabeth M. Rudnick, Miron Abramovici
    Compact Test Generation Using a Frozen Clock Testing Strategy. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2000, v:16, n:5, pp:703-717 [Journal]
  41. Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi
    A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:11, pp:1248-1256 [Journal]
  42. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
    Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:3, pp:311-322 [Journal]
  43. Dirk Niggemeyer, Elizabeth M. Rudnick
    Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:9, pp:1134-1146 [Journal]
  44. Elizabeth M. Rudnick, Janak H. Patel
    Efficient Techniques for Dynamic Test Sequence Compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:3, pp:323-330 [Journal]
  45. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
    Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:239-254 [Journal]
  46. Jue Wu, Elizabeth M. Rudnick
    Bridge fault diagnosis using stuck-at fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:489-495 [Journal]
  47. Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel
    An observability enhancement approach for improved testability and at-speed test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1051-1056 [Journal]
  48. Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
    A genetic algorithm framework for test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1034-1044 [Journal]
  49. Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty
    Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:471-489 [Journal]
  50. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
    Dynamic state traversal for sequential circuit test generation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:548-565 [Journal]
  51. Dirk Niggemeyer, Elizabeth M. Rudnick
    A data acquisition methodology for on-chip repair of embedded memories. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:560-576 [Journal]
  52. Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel
    Sequential circuit testability enhancement using a nonscan approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:333-338 [Journal]
  53. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
    Peak power estimation of VLSI circuits: new peak power measures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:435-439 [Journal]

  54. Sequential circuit test generation using dynamic state traversal. [Citation Graph (, )][DBLP]


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