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Sergio Bampi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alexandro M. S. Adário, Eduardo L. Roehe, Sergio Bampi
    Dynamically Reconfigurable Architecture for Image Processor Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:623-628 [Conf]
  2. Marcos R. Boschetti, Ivan Saraiva Silva, Sergio Bampi
    A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:242-247 [Conf]
  3. Jung Hyun Choi, Sergio Bampi
    OTA Amplifiers Design on Digital Sea-of-Transistors Array. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:776-777 [Conf]
  4. Alessandro Girardi, Sergio Bampi
    LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11106-11107 [Conf]
  5. Alex Panato, Sandro V. Silva, Flávio Rech Wagner, Marcelo O. Johann, Ricardo Reis, Sergio Bampi
    Design of Very Deep Pipelined Multipliers for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:52-57 [Conf]
  6. Sandro V. Silva, Sergio Bampi
    Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:32-37 [Conf]
  7. Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Ivan Saraiva Silva
    A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:210-213 [Conf]
  8. Marcos R. Boschetti, Sergio Bampi, Ivan Saraiva Silva
    Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:474-483 [Conf]
  9. Eric E. Fabris, Luigi Carro, Sergio Bampi
    Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1136-1138 [Conf]
  10. Luciano Volcan Agostini, Roger Porto, Sergio Bampi, Leandro Rosa, José Güntzel, Ivan Saraiva Silva
    High throughput architecture for H.264/AVC forward transforms block. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:320-323 [Conf]
  11. Eduardo A. C. da Costa, Sergio Bampi, José Monteiro
    A New Architecture for Signed Radix-2m Pure Array Multipliers. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:112-117 [Conf]
  12. Diogo Zandonai, Sergio Bampi, Marcel Bergerman
    ME64 - A Parallel Hardware Architecture for Motion Estimation Implemented in FPGA. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:317-326 [Conf]
  13. Alexandro M. S. Adário, Sergio Bampi
    Reconfigurable Computing: Viable Applications and Trends. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:583-594 [Conf]
  14. Jung Hyun Choi, Sergio Bampi
    CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:337-347 [Conf]
  15. Luigi Carro, Edgard de Faria Corrêa, R. Cardozo, Fernando Moraes, Sergio Bampi
    Exploiting reconfigurability for low-power control of embedded processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:421-424 [Conf]
  16. Eric E. Fabris, Luigi Carro, Sergio Bampi
    An analog signal interface with constant performance for SoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:773-776 [Conf]
  17. Luís Felipe Uebel, Sergio Bampi
    A Timing Model for VLSI CMOS Circuits Verification and Optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:439-442 [Conf]
  18. Juan Pablo Martinez Brito, Hamilton Klimach, Sergio Bampi
    A Design Methodology for Matching Improvement in Bandgap References. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:586-594 [Conf]
  19. Luciano Severino de Paula, Eric E. Fabris, Sergio Bampi, Altamiro Amadeu Susin
    A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:467-470 [Conf]
  20. Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi
    Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:445-446 [Conf]
  21. Tatiana G. S. dos Santos, Sergio Bampi
    Analyzing Instruction Prefetch Schemes in Superscalar Architectures. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  22. Arnaldo Azevedo, Luciano Volcan Agostini, Flávio Rech Wagner, Sergio Bampi
    Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:255-257 [Conf]
  23. Vagner S. Rosa, Eduardo A. C. da Costa, Sergio Bampi
    A High Performance Parallel FIR Filters Generation Tool. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:216-222 [Conf]
  24. Rafael R. dos Santos, Tatiana G. S. dos Santos, Maurício L. Pilla, Philippe Olivier Alexandre Navaux, Sergio Bampi, Mario Nemirovsky
    Complex Branch Profiling for Dynamic Conditional Execution. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2003, pp:28-35 [Conf]
  25. Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eduardo Conrad Jr., Sergio Bampi
    T-shaped association of transistors: modeling of multiple channel lengths and regular associations. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:21-26 [Conf]
  26. Eric E. Fabris, Luigi Carro, Sergio Bampi
    Modeling and designing high performance analog reconfigurable circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:49-54 [Conf]
  27. Alessandro Girardi, Sergio Bampi
    Power constrained design optimization of analog circuits based on physical gm/ID characteristics. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:89-93 [Conf]
  28. Vagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi
    An improved synthesis method for low power hardwired FIR filters. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:237-241 [Conf]
  29. Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi
    A band-pass Gm-C Filter design based on gm/ID methodology and characterization. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:232-237 [Conf]
  30. M. Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José C. Monteiro
    Design of a radix-2m hybrid array multiplier using carry save adder format. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:172-177 [Conf]
  31. Diogo Zandonai, Sergio Bampi, Marcel Bergerman
    ME64 - A Highly Scalable Hardware Parallel Architecture Motion Estimation in FPGA. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:93-98 [Conf]
  32. Eduardo A. C. da Costa, Sergio Bampi, José C. Monteiro
    A New Pipelined Array Architecture for Signed Multiplication. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:65-70 [Conf]
  33. Eric E. Fabris, Luigi Carro, Sergio Bampi
    A Universal High-Performance Analog Interface for Signal Processing SOCs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:137-0 [Conf]
  34. Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi
    Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:311-316 [Conf]
  35. Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi
    Applying the GM/ID method in the analysis and design of Miller Amplifier, Comparator and GM-C PASS-B. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:410-415 [Conf]
  36. Eduardo A. C. da Costa, José Monteiro, Sergio Bampi
    Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:307-0 [Conf]
  37. Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi
    A new array architecture for signed multiplication using Gray encoded radix-2m operands. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:118-132 [Journal]
  38. João Leonardo Fragoso, Eduardo Costa Pereira, Juergen Rochol, Sergio Bampi, Ricardo Reis
    Specification and design of an Ethernet Interface soft IP. [Citation Graph (0, 0)][DBLP]
    J. Braz. Comp. Soc., 2000, v:6, n:3, pp:5-12 [Journal]
  39. Luciano Volcan Agostini, Ivan Saraiva Silva, Sergio Bampi
    Parallel color space converters for JPEG image compression. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:4, pp:697-703 [Journal]
  40. Alessandro Girardi, Sergio Bampi
    AC analysis of an inverter amplifier using minimum-length trapezoidal association of transistors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:4, pp:665-671 [Journal]
  41. Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi
    Analysis and design of amplifiers and comparators in CMOS 0.35 mum technology. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2004, v:44, n:4, pp:657-664 [Journal]
  42. Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana G. S. dos Santos, Sergio Bampi, Altamiro Amadeu Susin
    FPGA Design of A H.264/AVC Main Profile Decoder for HDTV. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  43. Luciano Volcan Agostini, Sergio Bampi
    FPGA Based Architectures for H. 264/AVC Video Compression Standard. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
  44. Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi
    MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1617-1620 [Conf]
  45. Juan Pablo Martinez Brito, Sergio Bampi, Hamilton Klimach
    A 4-Bits Trimmed CMOS Bandgap Reference with an Improved Matching Modeling Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1911-1914 [Conf]
  46. Eric E. Fabris, Luigi Carro, Sergio Bampi
    Reconfigurable analog interface for mixed signal SOC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  47. Alessandro Girardi, F. P. Cortes, Sergio Bampi
    A tool for automatic design of analog circuits based on gm/ID methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  48. Luciano Volcan Agostini, Roger Porto, José Güntzel, Ivan Saraiva Silva, Sergio Bampi
    High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  49. Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger E. Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin
    FPGA Prototyping Strategy for a H.264/AVC Video Decoder. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:174-180 [Conf]
  50. Wagston T. Staehler, Eduardo A. Berriel, Altamiro Amadeu Susin, Sergio Bampi
    Architecture of an HDTV Intraframe Predictor for a H.264 Decoder. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:228-233 [Conf]
  51. Vagner S. Rosa, Eduardo Costa, Sergio Bampi
    A VHDL Generation Tool for Optimized Parallel FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:134-139 [Conf]
  52. Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi
    Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:52-57 [Conf]
  53. Leonardo L. de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José C. Monteiro, João Baptista Martins, Sergio Bampi, Ricardo Augusto da Luz Reis
    A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:25-39 [Conf]
  54. Sandro V. Silva, Sergio Bampi
    Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  55. Luciano Volcan Agostini, Ivan Saraiva Silva, Sergio Bampi
    Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:8, pp:487-497 [Journal]

  56. A high throughput and low cost diamond search architecture for HDTV motion estimation. [Citation Graph (, )][DBLP]


  57. A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video. [Citation Graph (, )][DBLP]


  58. HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV. [Citation Graph (, )][DBLP]


  59. Reusing Traces in a Dynamic Conditional Execution Architecture. [Citation Graph (, )][DBLP]


  60. A wide band CMOS differential voltage-controlled ring oscillator. [Citation Graph (, )][DBLP]


  61. A fully integrated CMOS RF front-end for a multi-band analog mixed-signal interface. [Citation Graph (, )][DBLP]


  62. Design of a digital FM demodulator based on a 2nddegree order all-digital phase-locked loop. [Citation Graph (, )][DBLP]


  63. Trim range limited by noise in bandgap voltage references. [Citation Graph (, )][DBLP]


  64. Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV. [Citation Graph (, )][DBLP]


  65. A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis. [Citation Graph (, )][DBLP]


  66. High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV. [Citation Graph (, )][DBLP]


  67. Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors. [Citation Graph (, )][DBLP]


  68. A 40mhz 70db gain variable gain amplifier design using the gm/id design method. [Citation Graph (, )][DBLP]


  69. High performance motion estimation architecture using efficient adder-compressors. [Citation Graph (, )][DBLP]


  70. High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV. [Citation Graph (, )][DBLP]


  71. An HDTV H.264 deblocking filter in FPGA with RGB video output. [Citation Graph (, )][DBLP]


  72. A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder. [Citation Graph (, )][DBLP]


  73. Motion Compensation Hardware Accelerator Architecture for H.264/AVC. [Citation Graph (, )][DBLP]


  74. High Throughput Hardware Architecture for Motion Estimation with 4: 1 Pel Subsampling Targeting Digital Television Applications. [Citation Graph (, )][DBLP]


  75. A High Performance H.264 Deblocking Filter. [Citation Graph (, )][DBLP]


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