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Allon Adir: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Allon Adir, Hezi Azatchi, Eyal Bin, Ofer Peled, Kirill Shoikhet
    A generic micro-architectural test plan approach for microprocessor verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:769-774 [Conf]
  2. Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy
    VLIW: a case study of parallelism verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:779-782 [Conf]
  3. Allon Adir, Roy Emek, Yoav Katz, Anatoly Koyfman
    DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:3-6 [Conf]
  4. Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv
    Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:84-93 [Journal]
  5. Allon Adir, Hagit Attiya, Gil Shurek
    Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:5, pp:502-515 [Journal]
  6. Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jaeger, Ofer Peled
    A Framework for the Validation of Processor Architecture Compliance. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:902-905 [Conf]

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