The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Hari Ananthan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hari Ananthan, Kaushik Roy
    A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:413-418 [Conf]
  2. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
    Double-gate SOI devices for low-power and high-performance applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:217-224 [Conf]
  3. Hari Ananthan, Chris H. Kim, Kaushik Roy
    Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:8-13 [Conf]
  4. Hari Ananthan, Aditya Bansal, Kaushik Roy
    FinFET SRAM - Device and Circuit Design Considerations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:511-516 [Conf]
  5. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
    Double-Gate SOI Devices for Low-Power and High-Performance Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:445-452 [Conf]

Search in 0.002secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002