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Lawrence T. Pillage: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage
    On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:207-212 [Conf]
  2. Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage
    A Gate-Delay Model for high-Speed CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:576-580 [Conf]
  3. Rohini Gupta, Lawrence T. Pillage
    OTTER: Optimal Termination of Transmission Lines Excluding Radiation. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:640-645 [Conf]
  4. Lawrence T. Pillage, Xueqing Huang, Ronald A. Rohrer
    AWEsim: Asymptotic Waveform Evaluation for Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:634-637 [Conf]
  5. Lawrence T. Pillage, Ronald A. Rohrer
    A Quadratic Metric with a Simple Solution Scheme for Initial Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:324-329 [Conf]
  6. Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage
    Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:165-170 [Conf]
  7. Curtis L. Ratzlaff, Nanda Gopal, Lawrence T. Pillage
    RICE: Rapid Interconnect Circuit Evaluator. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:555-560 [Conf]
  8. Dah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh
    Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:367-372 [Conf]
  9. Xueqing Zhang, Lawrence T. Pillage, Ronald A. Rohrer
    Efficient Final Placement Based on Nets-as-Points. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:578-581 [Conf]
  10. Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer
    Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:332-337 [Conf]
  11. Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage
    ETA: electrical-level timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:258-262 [Conf]
  12. Nanda Gopal, Dean P. Neikirk, Lawrence T. Pillage
    Evaluating RC-Interconnect Using Moment-Matching Approximations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:74-77 [Conf]
  13. Douglas R. Holberg, Santanu Dutta, Lawrence T. Pillage
    DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:546-549 [Conf]
  14. Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage
    AWE macromodels of VLSI interconnect for circuit simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:64-70 [Conf]
  15. S. Y. Kim, Emre Tuncer, Rohini Gupta, Byron Krauter, T. Savarino, Dean P. Neikirk, Lawrence T. Pillage
    An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:58-65 [Conf]
  16. Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage
    RC interconnect synthesis-a moment fitting approach. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:418-425 [Conf]
  17. Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pillage
    Domain Characterization of Transmission Line Models for Efficient Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:558-562 [Conf]
  18. Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage
    Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:729-736 [Journal]
  19. Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage
    Time-domain macromodels for VLSI interconnect analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1257-1270 [Journal]
  20. Lawrence T. Pillage, Ronald A. Rohrer
    Asymptotic waveform evaluation for timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:352-366 [Journal]
  21. Curtis L. Ratzlaff, Lawrence T. Pillage
    RICE: rapid interconnect circuit evaluation using AWE. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:763-776 [Journal]
  22. Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage
    Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1526-1535 [Journal]

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