The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Stephen Dean Brown: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jason Helge Anderson, Stephen Dean Brown
    Technology Mapping for Large Complex PLDs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:698-703 [Conf]
  2. Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic
    Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:427-432 [Conf]
  3. A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
    Design and Implementation of the NUMAchine Multiprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:66-69 [Conf]
  4. Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
    FPGA technology mapping: a study of optimality. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:427-432 [Conf]
  5. Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
    Incremental retiming for FPGA physical synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:433-438 [Conf]
  6. Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown
    A Multithreaded Soft Processor for SoPC Area Reduction. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:131-142 [Conf]
  7. Jason Helge Anderson, Stephen Dean Brown
    An LPGA with Foldable PLA-style Logic Blocks. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:244-252 [Conf]
  8. Mehrdad Eslami Dehkordi, Stephen Dean Brown
    Recursive circuit clustering for minimum delay and area. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:242- [Conf]
  9. Alireza Kaviani, Stephen Dean Brown
    Technology mapping issues for an FPGA with lookup tables and PLA-like blocks. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:60-66 [Conf]
  10. Alireza Kaviani, Stephen Dean Brown
    Hybrid FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:3-9 [Conf]
  11. Deshanand P. Singh, Stephen Dean Brown
    The case for registered routing switches in field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:161-169 [Conf]
  12. Deshanand P. Singh, Stephen Dean Brown
    Integrated retiming and placement for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:67-76 [Conf]
  13. Deshanand P. Singh, Stephen Dean Brown
    Constrained clock shifting for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:121-126 [Conf]
  14. Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
    FPGA PLB Evaluation using Quantified Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:19-24 [Conf]
  15. Valavan Manohararajah, Terry Borer, Stephen Dean Brown, Zvonko G. Vranesic
    Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:232-241 [Conf]
  16. Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown
    Post-Placement BDD-Based Decomposition for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:31-38 [Conf]
  17. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
    A Detailed Router for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:382-385 [Conf]
  18. Deshanand P. Singh, Stephen Dean Brown
    Incremental placement for layout driven optimizations on FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:752-759 [Conf]
  19. Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
    Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:135-142 [Conf]
  20. Benjamin Tseng, Jonathan Rose, Stephen Dean Brown
    Improving FPGA Routing Architectures Using Architecture and CAD Interactions. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:99-104 [Conf]
  21. R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
    The NUMAchine Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:487-496 [Conf]
  22. Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown
    Experiences with Soft-Core Processor Design. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  23. Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic
    On two-step routing for FPGAS. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:60-66 [Conf]
  24. Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
    FPGA Logic Synthesis Using Quantified Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    SAT, 2005, pp:444-450 [Conf]
  25. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
    Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:3-8 [Conf]
  26. Deshanand P. Singh, Stephen Dean Brown
    An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:41-50 [Conf]
  27. Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown
    Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:28-33 [Conf]
  28. Stephen Dean Brown
    FPGA Architectural Research: A Survey. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:9-15 [Journal]
  29. Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic
    Minimizing FPGA Interconnect Delays. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:16-23 [Journal]
  30. Stephen Dean Brown, Jonathan Rose
    FPGA and CPLD Architectures: A Tutorial. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:42-57 [Journal]
  31. Alireza Kaviani, Stephen Dean Brown
    The Hybrid Field-Programmable Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:2, pp:74-83 [Journal]
  32. Deshanand P. Singh, Stephen Dean Brown
    An area-efficient timing closure technique for FPGAs using Shannon's expansion. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:167-173 [Journal]
  33. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
    A detailed router for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:620-628 [Journal]
  34. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
    A stochastic model to predict the routability of field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1827-1838 [Journal]
  35. Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
    Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2331-2340 [Journal]
  36. Tomasz S. Czajkowski, Stephen Dean Brown
    Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:324-329 [Conf]
  37. Mehrdad Eslami Dehkordi, Stephen Dean Brown, Terry Borer
    Modular Partitioning for Incremental Compilation. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  38. Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
    Adaptive FPGAs: High-Level Architecture and a Synthesis Method. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  39. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
    Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:895-903 [Journal]

  40. BddCut: Towards Scalable Symbolic Cut Enumeration. [Citation Graph (, )][DBLP]


  41. Functionally linear decomposition and synthesis of logic circuits for FPGAs. [Citation Graph (, )][DBLP]


  42. Towards automated ECOs in FPGAs. [Citation Graph (, )][DBLP]


  43. Fast toggle rate computation for FPGA circuits. [Citation Graph (, )][DBLP]


  44. Enhancements to FPGA design methodology using streaming. [Citation Graph (, )][DBLP]


  45. Delay driven AIG restructuring using slack budget management. [Citation Graph (, )][DBLP]


  46. On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees. [Citation Graph (, )][DBLP]


  47. Incremental placement for structured ASICs using the transportation problem. [Citation Graph (, )][DBLP]


  48. Towards Compilation of Streaming Programs into FPGA Hardware. [Citation Graph (, )][DBLP]


Search in 0.003secs, Finished in 0.005secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002