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Publications of Author

1. Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
   Computation and Refinement of Statistical Bounds on Circuit Delay. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:348-353 [Conf]
   
2. Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov
   Circuit optimization using statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:321-324 [Conf]
   
3. Aseem Agarwal, Florentin Dartu, David Blaauw
   Statistical gate delay model considering multiple input switching. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:658-663 [Conf]
   
4. Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
   Statistical Timing Analysis Using Bounds. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10062-10067 [Conf]
   
5. Aseem Agarwal, Kaviraj Chopra, David Blaauw
   Statistical Timing Based Optimization using Gate Sizing. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:400-405 [Conf]
   
6. Aseem Agarwal, David Blaauw, Vladimir Zolotov
   Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2003, pp:900-907 [Conf]
   
7. Aseem Agarwal, David Blaauw, Vladimir Zolotov
   Statistical Clock Skew Analysis Considering Intra-Die Process Variations. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2003, pp:914-921 [Conf]
   
8. Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
   Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:16-21 [Conf]
   
9. Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
   Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:29-36 [Conf]
   
10. Aseem Agarwal, Vladimir Zolotov, David T. Blaauw
    Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1243-1260 [Journal]
    
11. Aseem Agarwal, Vladimir Zolotov, David Blaauw
    Statistical clock skew analysis considering intradie-process variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1231-1242 [Journal]
    
12. Aseem Agarwal, Kaviraj Chopra, David Blaauw
    Statistical Timing Based Optimization using Gate Sizing [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]