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Vladimir Zolotov:
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Publications of Author
- Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
Computation and Refinement of Statistical Bounds on Circuit Delay. [Citation Graph (0, 0)][DBLP] DAC, 2003, pp:348-353 [Conf]
- Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov
Circuit optimization using statistical static timing analysis. [Citation Graph (0, 0)][DBLP] DAC, 2005, pp:321-324 [Conf]
- Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
Post-route gate sizing for crosstalk noise reduction. [Citation Graph (0, 0)][DBLP] DAC, 2003, pp:954-957 [Conf]
- Hongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions. [Citation Graph (0, 0)][DBLP] DAC, 2005, pp:71-76 [Conf]
- Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao
Inductance 101: Analysis and Design Issues. [Citation Graph (0, 0)][DBLP] DAC, 2001, pp:329-334 [Conf]
- Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw
On-chip inductance modeling and analysis. [Citation Graph (0, 0)][DBLP] DAC, 2000, pp:63-68 [Conf]
- Dongwoo Lee, Vladimir Zolotov, David Blaauw
Static timing analysis using backward signal propagation. [Citation Graph (0, 0)][DBLP] DAC, 2004, pp:664-669 [Conf]
- Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov
ClariNet: a noise analysis tool for deep submicron design. [Citation Graph (0, 0)][DBLP] DAC, 2000, pp:233-238 [Conf]
- Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
A stochastic approach To power grid analysis. [Citation Graph (0, 0)][DBLP] DAC, 2004, pp:171-176 [Conf]
- Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo
Driver Modeling and Alignment for Worst-Case Delay Noise. [Citation Graph (0, 0)][DBLP] DAC, 2001, pp:720-725 [Conf]
- Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah
Criticality computation in parameterized statistical timing. [Citation Graph (0, 0)][DBLP] DAC, 2006, pp:63-68 [Conf]
- Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Optimal placement of power supply pads and pins. [Citation Graph (0, 0)][DBLP] DAC, 2004, pp:165-170 [Conf]
- Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . [Citation Graph (0, 0)][DBLP] DATE, 2002, pp:456-464 [Conf]
- Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
Statistical Timing Analysis Using Bounds. [Citation Graph (0, 0)][DBLP] DATE, 2003, pp:10062-10067 [Conf]
- Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer
False-Noise Analysis for Domino Circuits. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:784-789 [Conf]
- David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang
On-chip inductance modeling. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2000, pp:75-80 [Conf]
- Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown
Optimization objectives and models of variation for statistical gate sizing. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:313-316 [Conf]
- David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda
Slope Propagation in Static Timing Analysis. [Citation Graph (0, 0)][DBLP] ICCAD, 2000, pp:338-343 [Conf]
- Aseem Agarwal, David Blaauw, Vladimir Zolotov
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. [Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:900-907 [Conf]
- Aseem Agarwal, David Blaauw, Vladimir Zolotov
Statistical Clock Skew Analysis Considering Intra-Die Process Variations. [Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:914-921 [Conf]
- Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh
Pessimism reduction in crosstalk noise aware STA. [Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:954-961 [Conf]
- Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov
False-Noise Analysis using Logic Implications. [Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:515-0 [Conf]
- Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda
Delay noise pessimism reduction by logic correlations. [Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:160-167 [Conf]
- Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov
Gate sizing using incremental parameterized statistical timing analysis. [Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:1029-1036 [Conf]
- Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
A precorrected-FFT method for simulating on-chip inductance. [Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:221-227 [Conf]
- Amit Jain, David Blaauw, Vladimir Zolotov
Accurate delay computation for noisy waveform shapes. [Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:947-953 [Conf]
- D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, A. Ardelea, A. Patel
SOI Transistor Model for Fast Transient Simulation. [Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:120128- [Conf]
- Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Vectorless Analysis of Supply Noise Induced Delay Variation. [Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:184-192 [Conf]
- Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. [Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:705-712 [Conf]
- Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy
Noise propagation and failure criteria for VLSI designs. [Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:587-594 [Conf]
- Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
Table look-up based compact modeling for on-chip interconnect timing and noise analysis. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2003, pp:668-671 [Conf]
- Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju
Model and analysis for combined package and on-chip power grid simulation. [Citation Graph (0, 0)][DBLP] ISLPED, 2000, pp:179-184 [Conf]
- Jinjun Xiong, Vladimir Zolotov, Lei He
Robust extraction of spatial correlation. [Citation Graph (0, 0)][DBLP] ISPD, 2006, pp:2-9 [Conf]
- Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
Post-Route Gate Sizing for Crosstalk Noise Reduction. [Citation Graph (0, 0)][DBLP] ISQED, 2003, pp:171-176 [Conf]
- Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. [Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:158-0 [Conf]
- Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh
False-Noise Analysis Using Resolution Method. [Citation Graph (0, 0)][DBLP] ISQED, 2002, pp:437-0 [Conf]
- Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta
Static Electromigration Analysis for Signal Interconnects. [Citation Graph (0, 0)][DBLP] ISQED, 2003, pp:377-0 [Conf]
- Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sun Ku, Rajendran Panda
A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. [Citation Graph (0, 0)][DBLP] ISQED, 2004, pp:232-237 [Conf]
- Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh
Noise Injection and Propagation in High Performance Designs. [Citation Graph (0, 0)][DBLP] ISQED, 2002, pp:425-430 [Conf]
- Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:16-21 [Conf]
- Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:29-36 [Conf]
- Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal
Worst case clock skew under power supply variations. [Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:22-28 [Conf]
- Aseem Agarwal, Vladimir Zolotov, David T. Blaauw
Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1243-1260 [Journal]
- Aseem Agarwal, Vladimir Zolotov, David Blaauw
Statistical clock skew analysis considering intradie-process variations. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1231-1242 [Journal]
- David Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta
Static electromigration analysis for on-chip signal interconnects. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:39-48 [Journal]
- David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran
Slope propagation in static timing analysis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1180-1195 [Journal]
- Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
Postroute gate sizing for crosstalk noise reduction. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1670-1677 [Journal]
- Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda
Impact of stress-induced backflow on full-chip electromigration risk assessment. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1038-1046 [Journal]
- Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
Fast on-chip inductance simulation using a precorrected-FFT method. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:49-66 [Journal]
- Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
Optimal placement of power-supply pads and pins. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:144-154 [Journal]
- Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov
False-noise analysis using logic implications. [Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:3, pp:474-498 [Journal]
- Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi
Inductance model and analysis methodology for high-speed on-chip interconnect. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:730-745 [Journal]
Static timing: Back to our roots. [Citation Graph (, )][DBLP]
Statistical ordering of correlated timing quantities and its application for path ranking. [Citation Graph (, )][DBLP]
Statistical multilayer process space coverage for at-speed test. [Citation Graph (, )][DBLP]
Transistor sizing of custom high-performance digital circuits with parametric yield considerations. [Citation Graph (, )][DBLP]
Incremental Criticality and Yield Gradients. [Citation Graph (, )][DBLP]
Optimal Margin Computation for At-Speed Test. [Citation Graph (, )][DBLP]
Variation-aware performance verification using at-speed structural test and statistical timing. [Citation Graph (, )][DBLP]
Compact modeling of variational waveforms. [Citation Graph (, )][DBLP]
Statistical path selection for at-speed test. [Citation Graph (, )][DBLP]
Voltage binning under process variation. [Citation Graph (, )][DBLP]
Pre-ATPG path selection for near optimal post-ATPG process space coverage. [Citation Graph (, )][DBLP]
Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power. [Citation Graph (, )][DBLP]
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