The SCEAS System
Navigation Menu

Search the dblp DataBase


Kaviraj Chopra: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov
    Circuit optimization using statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:321-324 [Conf]
  2. David Blaauw, Kaviraj Chopra
    CAD tools for variation tolerance. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:766- [Conf]
  3. Kaviraj Chopra, Sarma B. K. Vrudhula
    Implicit pseudo boolean enumeration algorithms for input vector control. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:767-772 [Conf]
  4. Aseem Agarwal, Kaviraj Chopra, David Blaauw
    Statistical Timing Based Optimization using Gate Sizing. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:400-405 [Conf]
  5. Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan
    A Framework for Battery-Aware Sensor Management. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:962-967 [Conf]
  6. Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester
    An efficient static algorithm for computing the soft error rates of combinational circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:164-169 [Conf]
  7. Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester
    Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1023-1028 [Conf]
  8. Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao
    Analysis and modeling of CD variation for statistical static timing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:60-66 [Conf]
  9. Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester
    A new statistical max operation for propagating skewness in statistical timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:237-243 [Conf]
  10. Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj
    Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:240-0 [Conf]
  11. Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer
    Top-k Aggressors Sets in Delay Noise Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:174-179 [Conf]
  12. Aseem Agarwal, Kaviraj Chopra, David Blaauw
    Statistical Timing Based Optimization using Gate Sizing [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  13. Transistor-Specific Delay Modeling for SSTA. [Citation Graph (, )][DBLP]

  14. Victim alignment in crosstalk aware timing analysis. [Citation Graph (, )][DBLP]

  15. A statistical approach for full-chip gate-oxide reliability analysis. [Citation Graph (, )][DBLP]

Search in 0.002secs, Finished in 0.003secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002