The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Mohab Anis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, Shawki Areibi
    Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:480-485 [Conf]
  2. Hassan Hassan, Mohab Anis, Antoine El Daher, Mohamed I. Elmasry
    Activity Packing in FPGAs for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:212-217 [Conf]
  3. Akhilesh Kumar, Mohab Anis
    An analytical state dependent leakage power model for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:612-617 [Conf]
  4. Hratch Mangassarian, Mohab Anis
    On Statistical Timing Analysis with Inter- and Intra-Die Variations. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:132-137 [Conf]
  5. Akhilesh Kumar, Mohab Anis
    Dual-Vt FPGA design for leakage power reduction (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:272- [Conf]
  6. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:267- [Conf]
  7. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    Design and optimization of MOS current mode logic for parameter variations. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:33-38 [Conf]
  8. Mohab Anis, Mohamed I. Elmasry
    Self-timed MOS current mode logic for digital applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:113-116 [Conf]
  9. Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry
    High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:155-160 [Conf]
  10. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    LAP: a logic activity packing methodology for leakage power-tolerant FPGAs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:257-262 [Conf]
  11. Javid Jaffari, Mohab Anis
    Variability-aware device optimization under ION and leakage current constraints. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:119-122 [Conf]
  12. Akhilesh Kumar, Mohab Anis
    Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:735-740 [Conf]
  13. Ahmed Youssef, Tor Myklebust, Mohab Anis, Mohamed I. Elmasry
    A Low-Power Multi-Pin Maze Routing Methodology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:153-158 [Conf]
  14. Javid Jaffari, Mohab Anis
    Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:666-671 [Conf]
  15. Payam Ghafari, Ehsan Mirhadi, Mohab Anis, Shawki Areibi, Mohamed I. Elmasry
    A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:368-371 [Conf]
  16. Mohab Anis, Mohamed H. Abu-Rahma
    Leakage Current Variability in Nanometer Technologies, invited. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:60-63 [Conf]
  17. Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry
    Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:371-384 [Conf]
  18. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    Design and optimization of MOS current mode logic for parameter variations. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:417-437 [Journal]
  19. Mohab Anis, Shawki Areibi, Mohamed I. Elmasry
    Design and optimization of multithreshold CMOS (MTCMOS) circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1324-1342 [Journal]
  20. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    MOS current mode circuits: analysis, design, and variability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:885-898 [Journal]
  21. Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry
    POMR: a power-aware interconnect optimization methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:297-307 [Journal]
  22. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    Impact of technology scaling and process variations on RF CMOS devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:4, pp:275-282 [Journal]
  23. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    Low-power multi-threshold MCML: Analysis, design, and variability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:10, pp:1097-1104 [Journal]
  24. Mohamed H. Abu-Rahma, Mohab Anis
    Variability in VLSI Circuits: Sources and Design Considerations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3215-3218 [Conf]
  25. Rodrigo Jaramillo-Ramirez, Mohab Anis
    A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3724-3727 [Conf]
  26. Mohab Anis, Mohamed W. Allam, Mohamed I. Elmasry
    Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:71-78 [Journal]

  27. A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs. [Citation Graph (, )][DBLP]


  28. A methodology for statistical estimation of read access yield in SRAMs. [Citation Graph (, )][DBLP]


  29. Practical Monte-Carlo based timing yield estimation of digital circuits. [Citation Graph (, )][DBLP]


  30. Correlation controlled sampling for efficient variability analysis of analog circuits. [Citation Graph (, )][DBLP]


  31. On efficient Monte Carlo-based statistical static timing analysis of digital circuits. [Citation Graph (, )][DBLP]


  32. Adaptive sampling for efficient failure probability analysis of SRAM cells. [Citation Graph (, )][DBLP]


  33. Advanced IC technology - opportunities and challenges. [Citation Graph (, )][DBLP]


  34. Variability-aware design of subthreshold devices. [Citation Graph (, )][DBLP]


  35. Switching activity reduction in low power Booth multiplier. [Citation Graph (, )][DBLP]


  36. Timing yield estimation of digital circuits using a control variate technique. [Citation Graph (, )][DBLP]


  37. IR-drop management CAD techniques in FPGAs for power grid reliability. [Citation Graph (, )][DBLP]


  38. Discrete cooperative particle swarm optimization for FPGA placement. [Citation Graph (, )][DBLP]


Search in 0.117secs, Finished in 0.119secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002