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Mohamed I. Elmasry: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, Shawki Areibi
    Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:480-485 [Conf]
  2. O. A. Buset, Mohamed I. Elmasry
    ACE: A Hierarchical Graphical Interface for Architectual Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:537-542 [Conf]
  3. Catherine H. Gebotys, Mohamed I. Elmasry
    VLSI Design Synthesis with Testability. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:16-21 [Conf]
  4. Catherine H. Gebotys, Mohamed I. Elmasry
    Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:2-7 [Conf]
  5. Hassan Hassan, Mohab Anis, Antoine El Daher, Mohamed I. Elmasry
    Activity Packing in FPGAs for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:212-217 [Conf]
  6. Kambiz K. Moez, Mohamed I. Elmasry
    A 10-GHz 15-dB four-stage distributed amplifier in 0.18 µm CMOS process. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:405-409 [Conf]
  7. Nasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini, Haydar Hadi
    A Novel Analytical Model for Evaluation of Substrate Crosstalk in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:355-359 [Conf]
  8. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:267- [Conf]
  9. I. S. Abu-Khater, A. Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan
    Circuit/architecture for low-power high-performance 32-bit adder. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:74-0 [Conf]
  10. A. M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry
    A Low-Power High-Performance Embedded SRAM Macrocell. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:13-17 [Conf]
  11. Emad N. Farag, Mohamed I. Elmasry
    Low-Power Implementation of Discrete Cosine Transform. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:174-177 [Conf]
  12. Amr N. Hafez, Mohamed I. Elmasry
    A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:306-309 [Conf]
  13. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    Design and optimization of MOS current mode logic for parameter variations. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:33-38 [Conf]
  14. A. E. Hussein, Mohamed I. Elmasry
    Low power high speed analog-to-digital converter for wireless communications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:113-116 [Conf]
  15. Muhammad M. Khellah, Mohamed I. Elmasry
    Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:414-419 [Conf]
  16. Amr G. Wassal, M. Anwarul Hasan, Mohamed I. Elmasry
    Low-Power Design of Finite Field Multipliers for Wireless Applications. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:19-25 [Conf]
  17. Catherine H. Gebotys, Mohamed I. Elmasry
    A Global Optimization Approach for Architectural Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:258-261 [Conf]
  18. Nasser Masoumi, Safieddin Safavi-Naeini, Mohamed I. Elmasry
    An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using Microstrip Lines Theory. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:127-132 [Conf]
  19. Maitham Shams, Mohamed I. Elmasry
    Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:563-568 [Conf]
  20. Maitham Shams, Jo C. Ebergen, Mohamed I. Elmasry
    Optimizing CMOS Implementations of the C-element. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:700-705 [Conf]
  21. Nasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini
    A Fast Parametric Model for Contact-Substrate Coupling. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:69-76 [Conf]
  22. R. X. Gu, Mohamed I. Elmasry
    An All-N-Logic High-Speed Single-Phase Dynamic CMOS Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:7-10 [Conf]
  23. R. X. Gu, Mohamed I. Elmasry
    Power Dissipation in Deep Submicron CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:33-36 [Conf]
  24. K. M. Sharaf, Mohamed I. Elmasry
    BiCMOS Active-Pull-Down Non-Threshold Logic Cicuits for High-Speed Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:19-22 [Conf]
  25. L. Song, Mohamed I. Elmasry, Anthony Vannelli
    Analog neural network building blocks based on current mode subthreshold operation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2462-2465 [Conf]
  26. M. E. S. Elrabaa, Mohamed I. Elmasry
    Split-Gate Logic circuits for multi-threshold technologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:798-801 [Conf]
  27. A. M. Fahim, Mohamed I. Elmasry
    A Low-Voltage High-Performance Differential Static Logic (LVDSL) family. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:230-233 [Conf]
  28. A. M. Fahim, Mohamed I. Elmasry
    A low-power CMOS frequency synthesizer design methodology for wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:115-119 [Conf]
  29. Amr N. Hafez, Mohamed I. Elmasry
    A low power monolithic subsampled phase-locked loop architecture for wireless transceivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:549-552 [Conf]
  30. Maitham Shams, Mohamed I. Elmasry
    A formulation for quick evaluation and optimization of digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:326-329 [Conf]
  31. A. E. Hussein, Mohamed I. Elmasry
    Fractional-N frequency synthesizer for wireless communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:513-516 [Conf]
  32. D. A. F. Ei-Dib, Mohamed I. Elmasry
    Low-power register-exchange Viterbi decoder for high-speed wireless communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:737-740 [Conf]
  33. Mohab Anis, Mohamed I. Elmasry
    Self-timed MOS current mode logic for digital applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:113-116 [Conf]
  34. Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry
    High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:155-160 [Conf]
  35. Ayman ElSayed, Akbar Ali, Mohamed I. Elmasry
    Differential PLL for wireless applications using differential CMOS LC-VCO and differential charge pump. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:243-248 [Conf]
  36. Emad N. Farag, Ran-Hong Yan, Mohamed I. Elmasry
    A programmable power-efficient decimation filter for software radios. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:68-71 [Conf]
  37. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    LAP: a logic activity packing methodology for leakage power-tolerant FPGAs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:257-262 [Conf]
  38. Maitham Shams, Jo C. Ebergen, Mohamed I. Elmasry
    A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:93-96 [Conf]
  39. Ahmed Youssef, Tor Myklebust, Mohab Anis, Mohamed I. Elmasry
    A Low-Power Multi-Pin Maze Routing Methodology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:153-158 [Conf]
  40. Payam Ghafari, Ehsan Mirhadi, Mohab Anis, Shawki Areibi, Mohamed I. Elmasry
    A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:368-371 [Conf]
  41. Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry
    Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:371-384 [Conf]
  42. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    Design and optimization of MOS current mode logic for parameter variations. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:417-437 [Journal]
  43. Li Deng, Khaled Hassanein, Mohamed I. Elmasry
    Analysis of the correlation structure for a neural predictive model with application to speech recognition. [Citation Graph (0, 0)][DBLP]
    Neural Networks, 1994, v:7, n:2, pp:331-339 [Journal]
  44. Mohamed I. Elmasry
    Logic Design Using EFL Structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:9, pp:952-956 [Journal]
  45. Mohamed I. Elmasry, Philip M. Thompson
    Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:3, pp:250-258 [Journal]
  46. Arun Achyuthan, Mohamed I. Elmasry
    Mixed analog/digital hardware synthesis of artificial neural networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1073-1087 [Journal]
  47. Mohab Anis, Shawki Areibi, Mohamed I. Elmasry
    Design and optimization of multithreshold CMOS (MTCMOS) circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1324-1342 [Journal]
  48. Catherine H. Gebotys, Mohamed I. Elmasry
    Global optimization approach for architectural synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1266-1278 [Journal]
  49. Baher Haroun, Mohamed I. Elmasry
    Architectural synthesis for DSP silicon compilers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:431-447 [Journal]
  50. J. Paul Harvey, Mohamed I. Elmasry, Bosco Leung
    STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1402-1417 [Journal]
  51. Nasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini
    Fast and efficient parametric modeling of contact-to-substratecoupling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1282-1292 [Journal]
  52. Michael S. Obrecht, Mohamed I. Elmasry, Edwin L. Heasell
    TRASIM: compact and efficient two-dimensional transient simulator for arbitrary planar semiconductor devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:447-458 [Journal]
  53. Kevin S. B. Szabo, James M. Leask, Mohamed I. Elmasry
    Symbolic Layout for Bipolar and MOS VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:2, pp:202-210 [Journal]
  54. A. R. Teene, Mohamed I. Elmasry, David J. Roulston
    WATPC: A Computer-Aided Design Package for Digital Bipolar Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1982, v:1, n:4, pp:213-219 [Journal]
  55. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    MOS current mode circuits: analysis, design, and variability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:885-898 [Journal]
  56. Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry
    POMR: a power-aware interconnect optimization methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:297-307 [Journal]
  57. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    Impact of technology scaling and process variations on RF CMOS devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:4, pp:275-282 [Journal]
  58. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
    Low-power multi-threshold MCML: Analysis, design, and variability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:10, pp:1097-1104 [Journal]
  59. Kambiz K. Moez, Mohamed I. Elmasry
    Lumped-element analysis and design of CMOS distributed amplifiers with image impedance termination. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:10, pp:1136-1145 [Journal]
  60. A. Ismail, Mohamed I. Elmasry
    A termination technique for the averaging network of flash ADC's. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  61. Shaahin Hessabi, M. Y. Osman, Mohamed I. Elmasry
    Differential BiCMOS logic circuits: fault characterization and design-for-testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:437-445 [Journal]
  62. D. Zhang, Mohamed I. Elmasry
    VLSI compressor design with applications to digital neural networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:230-233 [Journal]
  63. Maitham Shams, Jo C. Ebergen, Mohamed I. Elmasry
    Modeling and comparing CMOS implementations of the C-element. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:563-567 [Journal]
  64. B. A. White, Mohamed I. Elmasry
    Low-power design of decimation filters for a digital IF receiver. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:339-345 [Journal]
  65. Muhammad M. Khellah, Mohamed I. Elmasry
    A low-power high-performance current-mode multiport SRAM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:590-598 [Journal]
  66. Mohab Anis, Mohamed W. Allam, Mohamed I. Elmasry
    Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:71-78 [Journal]

  67. A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs. [Citation Graph (, )][DBLP]


  68. Discrete cooperative particle swarm optimization for FPGA placement. [Citation Graph (, )][DBLP]


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