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Frank Liu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula
    Variational delay metrics for interconnect timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:381-384 [Conf]
  2. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
    Delay and slew metrics using the lognormal distribution. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:382-385 [Conf]
  3. Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter
    A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:186-189 [Conf]
  4. Frank Liu
    A practical method to estimate interconnect responses to variabilities. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:545-546 [Conf]
  5. Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
    Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:958-963 [Conf]
  6. Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze
    Integrated placement and skew optimization for rotary clocking. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:756-761 [Conf]
  7. Peter Feldmann, F. Liu
    Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:88-92 [Conf]
  8. Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
    A delay metric for RC circuits based on the Weibull distribution. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:620-624 [Conf]
  9. Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown
    A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:689-692 [Conf]
  10. Xiaoji Ye, Peng Li, Frank Liu
    Practical variation-aware interconnect delay and slew analysis for statistical timing verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:54-59 [Conf]
  11. Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif
    Full chip leakage estimation considering power supply and temperature variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:78-83 [Conf]
  12. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    Closed form expressions for extending step delay and slew metrics to ramp inputs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:24-31 [Conf]
  13. Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif
    Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:644-649 [Conf]
  14. Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu
    Test structures for delay variability. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:109- [Conf]
  15. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    PERI: a technique for extending delay and slew metrics to ramp inputs. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:57-62 [Conf]
  16. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
    Closed-form delay and slew metrics made easy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1661-1669 [Journal]
  17. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:509-516 [Journal]
  18. Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
    A delay metric for RC circuits based on the Weibull distribution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:443-447 [Journal]
  19. Frank Liu
    A General Framework for Spatial Correlation Modeling in VLSI Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:817-822 [Conf]
  20. Ritu Singhal, Asha Balijepalli, Anupama Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao
    Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:823-828 [Conf]
  21. Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
    The Impact of NBTI on the Performance of Combinational and Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:364-369 [Conf]
  22. Min Chen, Wei Zhao, Frank Liu, Yu Cao
    Fast statistical circuit analysis with finite-point based transistor model. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1391-1396 [Conf]
  23. Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
    Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  24. Ram Bhuwan Pandit, Juming Tang, Frank Liu, Galina Mikhaylenko
    A computer vision method to locate cold spots in foods in microwave sterilization processes. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 2007, v:40, n:12, pp:3667-3676 [Journal]
  25. Xiaoji Ye, Frank Liu, Peng Li
    Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:913-926 [Journal]
  26. Ganesh Venkataraman, Jiang Hu, Frank Liu
    Integrated Placement and Skew Optimization for Rotary Clocking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:149-158 [Journal]

  27. A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects. [Citation Graph (, )][DBLP]


  28. Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. [Citation Graph (, )][DBLP]


  29. Variability analysis under layout pattern-dependent rapid-thermal annealing process. [Citation Graph (, )][DBLP]


  30. Predicting variability in nanoscale lithography processes. [Citation Graph (, )][DBLP]


  31. An efficient method for statistical circuit simulation. [Citation Graph (, )][DBLP]


  32. Efficient computation of current flow in signal wires for reliability analysis. [Citation Graph (, )][DBLP]


  33. Modeling of layout-dependent stress effect in CMOS design. [Citation Graph (, )][DBLP]


  34. A Root-Finding Method for Assessing SRAM Stability. [Citation Graph (, )][DBLP]


  35. MAISE: An Interconnect Simulation Engine for Timing and Noise Analysis. [Citation Graph (, )][DBLP]


  36. Guest Editors' Introduction: Compact Variability Modeling in Scaled CMOS Design. [Citation Graph (, )][DBLP]


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