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Anuradha Agarwal:
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Publications of Author
- Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
Fast and accurate parasitic capacitance models for layout-aware. [Citation Graph (0, 0)][DBLP] DAC, 2004, pp:145-150 [Conf]
- Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
Accurate Estimation of Parasitic Capacitances in Analog Circuits. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1364-1365 [Conf]
- Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:604-609 [Conf]
- Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:482-487 [Conf]
- Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2004, pp:271-276 [Conf]
- Anuradha Agarwal, Ranga Vemuri
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. [Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:430-436 [Conf]
- Anuradha Agarwal, Ranga Vemuri
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. [Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:444-452 [Conf]
- Huiying Yang, Anuradha Agarwal, Ranga Vemuri
Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. [Citation Graph (0, 0)][DBLP] ISVLSI, 2005, pp:71-76 [Conf]
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