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Ravishankar Arunachalam:
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Publications of Author
- Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi
False Coupling Interactions in Static Timing Analysis. [Citation Graph (0, 0)][DBLP] DAC, 2001, pp:726-731 [Conf]
- Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
TACO: timing analysis with coupling. [Citation Graph (0, 0)][DBLP] DAC, 2000, pp:266-269 [Conf]
- Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
Determination of worst-case aggressor alignment for delay calculation. [Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:212-219 [Conf]
- Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi
CMOS Gate Delay Models for General RLC Loading. [Citation Graph (0, 0)][DBLP] ICCD, 1997, pp:224-229 [Conf]
- Siddharth Garg, Siddharth Tata, Ravishankar Arunachalam
Static Transition Probability Analysis Under Uncertainty. [Citation Graph (0, 0)][DBLP] ICCD, 2004, pp:380-386 [Conf]
- Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif
Optimal shielding/spacing metrics for low power design. [Citation Graph (0, 0)][DBLP] ISVLSI, 2003, pp:167-172 [Conf]
- Aniket, Ravishankar Arunachalam
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits. [Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:479-484 [Conf]
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