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Ronald D. Blanton: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi
    False Coupling Interactions in Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:726-731 [Conf]
  2. Kumar N. Dwarakanath, Ronald D. Blanton
    Universal fault simulation using fault tuples. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:786-789 [Conf]
  3. Ronald D. Blanton, John P. Hayes
    Efficient Testing of Tree Circuits. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:176-185 [Conf]
  4. Ronald D. Blanton, John P. Hayes
    Properties of the Input Pattern Fault Model. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:372-380 [Conf]
  5. Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton
    Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:173-178 [Conf]
  6. Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani
    Synthesis of Self-Testing Finite State Machines from High-Level Specifications. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:757-766 [Conf]
  7. Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels
    Fault Tuples in Diagnosis of Deep-Submicron Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:233-241 [Conf]
  8. Nilmoni Deb, Ronald D. Blanton
    Analysis of failure sources in surface-micromachined MEMS. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:739-749 [Conf]
  9. Rao Desineni, Kumar N. Dwarakanath, Ronald D. Blanton
    Universal test generation using fault tuples. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:812-819 [Conf]
  10. Tao Jiang, Ronald D. Blanton
    Particulate failures for surface-micromachined MEMS. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:329-337 [Conf]
  11. Abhijeet Kolpekwar, Ronald D. Blanton
    Development of a MEMS Testing Methodology. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:923-931 [Conf]
  12. Abhijeet Kolpekwar, Ronald D. Blanton, David Woodilla
    Failure modes for stiction in surface-micromachined MEMS. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:551-556 [Conf]
  13. Abhijeet Kolpekwar, Chris S. Kellen, Ronald D. Blanton
    MEMS fault model generation using CARAMEL. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:557-0 [Conf]
  14. Rahul Kundu, Ronald D. Blanton
    Identification of crosstalk switch failures in domino CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:502-509 [Conf]
  15. Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly
    To DFT or Not to DFT? [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:557-566 [Conf]
  16. Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly
    Modeling the Economics of Testing: A DFT Perspective. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:1, pp:29-41 [Journal]
  17. Ronald D. Blanton, John P. Hayes
    Testability of Convergent Tree Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:950-963 [Journal]
  18. Ronald D. Blanton, Kumar N. Dwarakanath, Rao Desineni
    Defect Modeling Using Fault Tuples. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2450-2464 [Journal]
  19. Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton
    Test vector generation for charge sharing failures in dynamic logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1502-1508 [Journal]
  20. Ronald D. Blanton, John P. Hayes
    On the properties of the input pattern fault model. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:1, pp:108-124 [Journal]
  21. Ronald D. Blanton, John P. Hayes
    On the design of fast, easily testable ALU's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:220-223 [Journal]

  22. Automated Testability Enhancements for Logic Brick Libraries. [Citation Graph (, )][DBLP]


  23. Physically-Aware N-Detect Test Pattern Selection. [Citation Graph (, )][DBLP]


  24. The input pattern fault model and its application. [Citation Graph (, )][DBLP]


  25. Statistical Test Compaction Using Binary Decision Trees. [Citation Graph (, )][DBLP]


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