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## Search the dblp DataBase
Lawrence T. Pileggi:
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## Publications of Author- Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi
**False Coupling Interactions in Static Timing Analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:726-731 [Conf] - Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
**TACO: timing analysis with coupling.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:266-269 [Conf] - Michael W. Beattie, Lawrence T. Pileggi
**Inductance 101: Modeling and Extraction.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:323-328 [Conf] - Michael W. Beattie, Lawrence T. Pileggi
**Modeling Magnetic Coupling for On-Chip Interconnect.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:335-340 [Conf] - Michael W. Beattie, Lawrence T. Pileggi
**Bounds for BEM Capacitance Extraction.**[Citation Graph (0, 0)][DBLP] DAC, 1997, pp:133-136 [Conf] - Michael W. Beattie, Lawrence T. Pileggi
**IC Analyses Including Extracted Inductance Models.**[Citation Graph (0, 0)][DBLP] DAC, 1999, pp:915-920 [Conf] - Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer
**Design closure (panel session): hope or hype?**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:176-177 [Conf] - Florentin Dartu, Lawrence T. Pileggi
**Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling.**[Citation Graph (0, 0)][DBLP] DAC, 1997, pp:46-51 [Conf] - Florentin Dartu, Lawrence T. Pileggi
**TETA: Transistor-Level Engine for Timing Analysis.**[Citation Graph (0, 0)][DBLP] DAC, 1998, pp:595-598 [Conf] - Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi
**RC-Interconnect Macromodels for Timing Simulation.**[Citation Graph (0, 0)][DBLP] DAC, 1996, pp:544-547 [Conf] - Abbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi
**Fast, cheap and under control: the next implementation fabric.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:354-355 [Conf] - Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi
**Architecture-aware FPGA placement using metric embedding.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:460-465 [Conf] - Rohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi
**The Elmore Delay as a Bound for RC Trees with Generalized Input Signals.**[Citation Graph (0, 0)][DBLP] DAC, 1995, pp:364-369 [Conf] - Satrajit Gupta, Lawrence T. Pileggi
**CHIME: coupled hierarchical inductance model evaluation.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:800-805 [Conf] - Zhijiang He, Mustafa Celik, Lawrence T. Pileggi
**SPIE: Sparse Partial Inductance Extraction.**[Citation Graph (0, 0)][DBLP] DAC, 1997, pp:137-140 [Conf] - Rony Kay, Lawrence T. Pileggi
**PRIMO: Probability Interpretation of Moments for Delay Calculation.**[Citation Graph (0, 0)][DBLP] DAC, 1998, pp:463-468 [Conf] - V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi
**Design methodology for IC manufacturability based on regular logic-bricks.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:353-358 [Conf] - V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi
**Routing architecture exploration for regular fabrics.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:204-207 [Conf] - Byron Krauter, Rohini Gupta, John Willis, Lawrence T. Pileggi
**Transmission Line Synthesis.**[Citation Graph (0, 0)][DBLP] DAC, 1995, pp:358-363 [Conf] - Byron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T. Pileggi
**A Sparse Image Method for BEM Capacitance Extraction.**[Citation Graph (0, 0)][DBLP] DAC, 1996, pp:357-362 [Conf] - Jiayong Le, Xin Li, Lawrence T. Pileggi
**STAC: statistical timing analysis with correlation.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:343-348 [Conf] - Xin Li, Jiayong Le, Lawrence T. Pileggi
**Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:103-108 [Conf] - Xin Li, Peng Li, Yang Xu, Lawrence T. Pileggi
**Analog and RF circuit macromodels for system-level analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:478-483 [Conf] - Peng Li, Lawrence T. Pileggi
**NORM: compact model order reduction of weakly nonlinear systems.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:472-477 [Conf] - Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, Lawrence T. Pileggi
**A frequency relaxation approach for analog/RF system-level simulation.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:842-847 [Conf] - Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi
**Min/max On-Chip Inductance Models and Delay Metrics.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:341-346 [Conf] - Tao Lin, Michael W. Beattie, Lawrence T. Pileggi
**On the efficacy of simplified 2D on-chip inductance models.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:757-762 [Conf] - Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas
**Impact of interconnect variations on the clock skew of a gigahertz microprocessor.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:168-171 [Conf] - Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
[Citation Graph (0, 0)][DBLP]*ftd*: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models. DAC, 1998, pp:469-472 [Conf] - Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
**Model Order-Reduction of RC(L) Interconnect Including Variational Analysis.**[Citation Graph (0, 0)][DBLP] DAC, 1999, pp:201-206 [Conf] - Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi
**Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization.**[Citation Graph (0, 0)][DBLP] DAC, 1995, pp:690-695 [Conf] - Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, V. Rovner, K. Y. Tong
**Exploring regular fabrics to optimize the performance-cost trade-off.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:782-787 [Conf] - Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi
**An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response.**[Citation Graph (0, 0)][DBLP] DAC, 1996, pp:611-616 [Conf] - Yang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi
**OPERA: optimization with ellipsoidal uncertainty for robust analog IC design.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:632-637 [Conf] - Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd
**ORACLE: optimization with recourse of analog circuits including layout extraction.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:151-154 [Conf] - Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma
**Correlation-aware statistical timing analysis with non-gaussian delay distributions.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:77-82 [Conf] - Hui Zheng, Lawrence T. Pileggi
**Modeling and analysis of regular symmetrically structured power/ground distribution networks.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:395-398 [Conf] - Michael W. Beattie, Lawrence T. Pileggi
**Efficient inductance extraction via windowing.**[Citation Graph (0, 0)][DBLP] DATE, 2001, pp:430-436 [Conf] - Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi
**A Linear-Centric Simulation Framework for Parametric Fluctuations.**[Citation Graph (0, 0)][DBLP] DATE, 2002, pp:568-575 [Conf] - Peng Li, Lawrence T. Pileggi
**A Linear-Centric Modeling Approach to Harmonic Balance Analysis.**[Citation Graph (0, 0)][DBLP] DATE, 2002, pp:634-639 [Conf] - Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi
**An Interconnect Channel Design Methodology for High Performance Integrated Circuits.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1138-1143 [Conf] - Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit
**Heterogeneous Programmable Logic Block Architectures.**[Citation Graph (0, 0)][DBLP] DATE, 2003, pp:11118-11119 [Conf] - Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi
**Exploring Logic Block Granularity for Regular Fabrics.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:468-473 [Conf] - Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
**Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:958-963 [Conf] - Tao Lin, Michael W. Beattie, Lawrence T. Pileggi
**On-Chip Inductance Models: 3D or Not 3D?**[Citation Graph (0, 0)][DBLP] DATE, 2002, pp:1112- [Conf] - Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
**Congestion-Aware Logic Synthesis.**[Citation Graph (0, 0)][DBLP] DATE, 2002, pp:664-671 [Conf] - Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi
**Noise Macromodel for Radio Frequency Integrated Circuits.**[Citation Graph (0, 0)][DBLP] DATE, 2003, pp:10150-10155 [Conf] - Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter
**Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses.**[Citation Graph (0, 0)][DBLP] DATE, 2002, pp:628-633 [Conf] - Aneesh Koorapaty, Lawrence T. Pileggi
**Modular, Fabric-Specific Synthesis for Programmable Architectures.**[Citation Graph (0, 0)][DBLP] FPL, 2002, pp:132-141 [Conf] - Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit
**Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics.**[Citation Graph (0, 0)][DBLP] FPL, 2003, pp:426-436 [Conf] - Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
**S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1999, pp:60-63 [Conf] - Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
**Bounding the efforts on congestion optimization for physical synthesis.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2003, pp:7-10 [Conf] - Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiao-Dong Yang, Sangwoo Kim, Stephan Mueller, Hendrik Mau, Lawrence T. Pileggi
**A fast simulation approach for inductive effects of VLSI interconnects.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2003, pp:108-111 [Conf] - Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi
**Hierarchical Interconnect Circuit Models.**[Citation Graph (0, 0)][DBLP] ICCAD, 2000, pp:215-221 [Conf] - Michael W. Beattie, Lawrence T. Pileggi
**Electromagnetic parasitic extraction via a multipole method with hierarchical refinement.**[Citation Graph (0, 0)][DBLP] ICCAD, 1999, pp:437-444 [Conf] - Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi
**A power aware system level interconnect design methodology for latency-insensitive systems.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:275-282 [Conf] - Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
**A hierarchical decomposition methodology for multistage clock circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:266-273 [Conf] - Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi
**Determination of worst-case aggressor alignment for delay calculation.**[Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:212-219 [Conf] - Rohini Gupta, Lawrence T. Pileggi
**Constrained multivariable optimization of transmission lines with general topologies.**[Citation Graph (0, 0)][DBLP] ICCAD, 1995, pp:130-137 [Conf] - Byron Krauter, Lawrence T. Pileggi
**Generating sparse partial inductance matrices with guaranteed stability.**[Citation Graph (0, 0)][DBLP] ICCAD, 1995, pp:45-52 [Conf] - Peng Li, Lawrence T. Pileggi
**Efficient harmonic balance simulation using multi-level frequency decomposition.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:677-682 [Conf] - Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas
**Projection-based performance modeling for inter/intra-die variations.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:721-727 [Conf] - Peng Li, Xin Li, Yang Xu, Lawrence T. Pileggi
**A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:454-462 [Conf] - Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi
**Asymptotic probability extraction for non-normal distributions of circuit performance.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:2-9 [Conf] - Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra
**Efficient full-chip thermal modeling and analysis.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:319-326 [Conf] - Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih Chen, Wanju Chiang
**Performance-centering optimization for system-level analog design exploration.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:422-429 [Conf] - Xin Li, Peng Li, Lawrence T. Pileggi
**Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:806-812 [Conf] - Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan
**Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:491-496 [Conf] - Tao Lin, Emrah Acar, Lawrence T. Pileggi
**h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response.**[Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:19-25 [Conf] - Tao Lin, Lawrence T. Pileggi
**Throughput-driven IC communication fabric synthesis.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:274-279 [Conf] - Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi
**Robust analog/RF circuit design with projection-based posynomial modeling.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:855-862 [Conf] - Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi
**Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:844-851 [Conf] - Noel Menezes, Ross Baldick, Lawrence T. Pileggi
**A sequential quadratic programming approach to concurrent gate and wire sizing.**[Citation Graph (0, 0)][DBLP] ICCAD, 1995, pp:144-151 [Conf] - Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
**PRIMA: passive reduced-order interconnect macromodeling algorithm.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:58-65 [Conf] - Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
**Practical considerations for passive reduction of RLC circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 1999, pp:214-220 [Conf] - Lawrence T. Pileggi
**Coping with RC(L) interconnect design headaches.**[Citation Graph (0, 0)][DBLP] ICCAD, 1995, pp:246-253 [Conf] - Hui Zheng, Lawrence T. Pileggi
**Robust and passive model order reduction for circuits containing susceptance elements.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:761-766 [Conf] - Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi
**CMOS Gate Delay Models for General RLC Loading.**[Citation Graph (0, 0)][DBLP] ICCD, 1997, pp:224-229 [Conf] - Peng Li, Yangdong Deng, Lawrence T. Pileggi
**Temperature-Dependent Optimization of Cache Leakage Power Dissipation.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:7-12 [Conf] - Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi
**Clustering and Load Balancing for Buffered Clock Tree Synthesis.**[Citation Graph (0, 0)][DBLP] ICCD, 1997, pp:217-223 [Conf] - Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje
**Overcoming wireload model uncertainty during physical design.**[Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:182-189 [Conf] - Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi
**EWA: exact wiring-sizing algorithm.**[Citation Graph (0, 0)][DBLP] ISPD, 1997, pp:178-185 [Conf] - Tao Lin, Lawrence T. Pileggi
**RC(L) interconnect sizing with second order considerations via posynomial programming.**[Citation Graph (0, 0)][DBLP] ISPD, 2001, pp:16-21 [Conf] - Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi
**An architectural exploration of via patterned gate arrays.**[Citation Graph (0, 0)][DBLP] ISPD, 2003, pp:184-189 [Conf] - Lawrence T. Pileggi
**Timing metrics for physical design of deep submicron technologies.**[Citation Graph (0, 0)][DBLP] ISPD, 1998, pp:28-33 [Conf] - Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
**Understanding and addressing the impact of wiring congestion during technology mapping.**[Citation Graph (0, 0)][DBLP] ISPD, 2002, pp:131-136 [Conf] - Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi
**Time-Domain Simulation of Variational Interconnect Models.**[Citation Graph (0, 0)][DBLP] ISQED, 2002, pp:419-424 [Conf] - Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu
**Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations.**[Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:431-436 [Conf] - E. Malley, A. Salinas, K. Ismail, Lawrence T. Pileggi
**Power Comparison of Throughput Optimized IC Busses.**[Citation Graph (0, 0)][DBLP] ISVLSI, 2003, pp:35-44 [Conf] - Rohini Gupta, Byron Krauter, Lawrence T. Pileggi
**On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1996, pp:150-155 [Conf] - Hui Zheng, Byron Krauter, Lawrence T. Pileggi
**Electrical Modeling of Integrated-Package Power and Ground Distributions.**[Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2003, v:20, n:3, pp:24-31 [Journal] - Emrah Acar, Florentin Dartu, Lawrence T. Pileggi
**TETA: transistor-level waveform evaluation for timing analysis.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:605-616 [Journal] - Michael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi
**Equipotential shells for efficient inductance extraction.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:70-79 [Journal] - Michael W. Beattie, Lawrence T. Pileggi
**Parasitics extraction with multipole refinement.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:288-292 [Journal] - Michael W. Beattie, Lawrence T. Pileggi
**Error bounds for capacitance extraction via window techniques.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:311-321 [Journal] - Mustafa Celik, Lawrence T. Pileggi
**Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:293-300 [Journal] - Florentin Dartu, Noel Menezes, Lawrence T. Pileggi
**Performance computation for precharacterized CMOS gates with RC loads.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:544-553 [Journal] - Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje
**An analysis of the wire-load model uncertainty problem.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:23-31 [Journal] - Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pileggi
**Domain characterization of transmission line models and analyses.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:184-193 [Journal] - Rohini Gupta, Byron Krauter, Lawrence T. Pileggi
**Transmission line synthesis via constrained multivariable optimization.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:6-19 [Journal] - Rohini Gupta, Bogdan Tutuianu, Lawrence T. Pileggi
**The Elmore delay as a bound for RC trees with generalized input signals.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:95-104 [Journal] - Rony Kay, Lawrence T. Pileggi
**EWA: efficient wiring-sizing algorithm for signal nets and clock nets.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:40-49 [Journal] - Peng Li, Lawrence T. Pileggi
**Efficient per-nonlinearity distortion analysis for analog and RF circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1297-1309 [Journal] - Peng Li, Lawrence T. Pileggi
**Compact reduced-order modeling of weakly nonlinear analog and RF circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:184-203 [Journal] - Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra
**IC thermal simulation and modeling via efficient multigrid-based approaches.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1763-1776 [Journal] - Noel Menezes, Ross Baldick, Lawrence T. Pileggi
**A sequential quadratic programming approach to concurrent gate and wire sizing.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:867-881 [Journal] - Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
**PRIMA: passive reduced-order interconnect macromodeling algorithm.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:645-654 [Journal] - Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
**Global and local congestion optimization in technology mapping.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:498-505 [Journal] - Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi
**Post-processing of clock trees via wiresizing and buffering for robust design.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:691-701 [Journal] - Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi
**Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:2, pp:210-215 [Journal] - Xin Li, Lawrence T. Pileggi
**Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:928-933 [Conf] - Jian Wang, Xin Li, Lawrence T. Pileggi
**Parameterized Macromodeling for Analog System-Level Design Exploration.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:940-943 [Conf] - Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
**Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction**[Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal] - Rohini Gupta, John Willis, Lawrence T. Pileggi
**Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:457-463 [Journal] - Michael W. Beattie, Lawrence T. Pileggi
**On-chip induction modeling: basics and advanced methods.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:712-729 [Journal] **Creating an affordable 22nm node using design-lithography co-optimization.**[Citation Graph (, )][DBLP]**SRAM parametric failure analysis.**[Citation Graph (, )][DBLP]**Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.**[Citation Graph (, )][DBLP]**Synthesis of Regular Logic Bricks for Robust IC Design.**[Citation Graph (, )][DBLP]**Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection.**[Citation Graph (, )][DBLP]**Reducing variability in chip-multiprocessors with adaptive body biasing.**[Citation Graph (, )][DBLP]
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