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Asim J. Al-Khalili: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili
    A Module Generator for Optimized CMOS Buffers. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:245-250 [Conf]
  2. F. Rouatbi, Baher Haroun, Asim J. Al-Khalili
    Power estimation tool for sub-micron CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:204-209 [Conf]
  3. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
    A Low Power Approach to Floating Point Adder Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:178-185 [Conf]
  4. Asim J. Al-Khalili
    A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers. [Citation Graph (0, 0)][DBLP]
    ICN/ICONS/MCL, 2006, pp:183- [Conf]
  5. Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri
    Area Efficient Computing Structures for Concurrent Error Detection in Systolic Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:484-491 [Conf]
  6. Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri
    Design Methodology for Fault-Tolerant Systolic Array Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1992, pp:267-274 [Conf]
  7. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
    An IEEE Compliant Floating Point MAF. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:149-160 [Conf]
  8. C. J. Macleod, Asim J. Al-Khalili
    An On-Line Optimization Procedure for an Urban Traffic System. [Citation Graph (0, 0)][DBLP]
    Optimization Techniques, 1973, pp:31-41 [Conf]
  9. Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri
    On the Design of Optimal Fault-Tolerant Systolic Array Architecures. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:352-357 [Conf]
  10. Asim J. Al-Khalili, Aiping Hu
    Design of a 32-bit squarer - exploiting addition redundancy. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:325-328 [Conf]
  11. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
    Power implications of precision limited arithmetic in floating point FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:165-168 [Conf]
  12. Shaoqiang Bi, Wei Wang, Asim J. Al-Khalili
    Modulo deflation in (2n+1, 2n, 2n-1) converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:429-432 [Conf]
  13. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
    Energy delay analysis of partial product reduction methods for parallel multiplier implementation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:201-204 [Conf]
  14. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
    Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:235-238 [Conf]
  15. Shaoqiang Bi, Warren J. Gross, Wei Wang, Asim J. Al-Khalili, M. N. S. Swamy
    An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:396-399 [Conf]
  16. Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri
    Design of optimal systolic arrays: a systematic approach. [Citation Graph (0, 0)][DBLP]
    SPDP, 1990, pp:166-173 [Conf]
  17. Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
    Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:119-125 [Conf]
  18. Jacob Augustine, William E. Lynch, Yuke Wang, Asim J. Al-Khalili
    Lossy Compression of Images Using Logic Minimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:538-543 [Conf]
  19. R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili
    A Low Power Floating Point Accumulator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:330-0 [Conf]
  20. Asim J. Al-Khalili
    An Algorithm for an Intelligent Arabic Computer Terminal. [Citation Graph (0, 0)][DBLP]
    International Journal of Man-Machine Studies, 1984, v:20, n:4, pp:331-341 [Journal]
  21. Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili
    A module generator for optimized CMOS buffers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1028-1046 [Journal]
  22. Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili
    Technology-portable analytical model for DSM CMOS inverter transition-time estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1177-1187 [Journal]
  23. Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili
    Delay analysis of CMOS gates using modified logical effort model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:937-947 [Journal]
  24. Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
    Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1637-1643 [Journal]
  25. Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria
    Zero skew differential clock distribution network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  26. An interconnect-aware delay model for dynamic voltage scaling in NM technologies. [Citation Graph (, )][DBLP]


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