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C. Y. Roger Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Thomas D. C. Little, C. Y. Roger Chen, C. S. Chang, P. Bruce Berra
    Multimedia Synchronization. [Citation Graph (2, 10)][DBLP]
    IEEE Data Eng. Bull., 1991, v:14, n:3, pp:26-35 [Journal]
  2. Mohammed Aloqeely, C. Y. Roger Chen
    Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:155-160 [Conf]
  3. Bradley S. Carlson, C. Y. Roger Chen
    Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:361-366 [Conf]
  4. C. Y. Roger Chen, Michael Z. Moricz
    Datapath Scheduling for Two-Level Pipelining. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:603-606 [Conf]
  5. Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
    Timing Driven Placement using Physical Net Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:780-783 [Conf]
  6. Cliff Yungchin Hou, C. Y. Roger Chen
    A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:594-599 [Conf]
  7. Uminder Singh, C. Y. Roger Chen
    A Transistor Reordering Technique for Gate Matrix Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:462-467 [Conf]
  8. Muhammad K. Dhodhi, Imtiaz Ahmad, C. Y. Roger Chen
    Synthesis of Application-Specific Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:671- [Conf]
  9. Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian
    Transistor Chaining in CMOS Leaf Cells of Planar Topology. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:194-199 [Conf]
  10. Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
    A sensitivity based placer for standard cells. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:193-196 [Conf]
  11. Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
    A novel technique for sea of gates global routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:71-74 [Conf]
  12. Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
    A novel ultra-fast heuristic for VLSI CAD steiner trees. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:192-197 [Conf]
  13. P. Bruce Berra, C. Y. Roger Chen, Arif Ghafoor, Thomas D. C. Little
    Issues in Networking and Data Management of Distributed Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    HPDC, 1992, pp:4-15 [Conf]
  14. Tacettin Kiprulu, Dikran S. Meliksetian, C. Y. Roger Chen
    Smoothing Algorithms for the Delivery of Compressed Video. [Citation Graph (0, 0)][DBLP]
    ICC (3), 1997, pp:1330-1334 [Conf]
  15. Imtiaz Ahmad, C. Y. Roger Chen
    Post-Processor for Data Path Synthesis Using Multiport Memories. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:276-279 [Conf]
  16. Cliff Yungchin Hou, C. Y. Roger Chen
    A Hierarchical Methodology to Improve Channel Routing by Pin Permutation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:440-443 [Conf]
  17. Naresh Sehgal, C. Y. Roger Chen, John M. Acken
    An object-oriented cell library manager. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:750-753 [Conf]
  18. Qinghong Wu, C. Y. Roger Chen, John M. Acken
    Efficent Boolean Matching Algorithm for Cell Libraries. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:36-39 [Conf]
  19. C. Y. Roger Chen, Kingsley C. Nwosu, P. Bruce Berra
    Modeling and Storage Allocation Strategies for Homogeneous Parallel Access Storage Devices in Real Time Multimedia Information Processing. [Citation Graph (0, 0)][DBLP]
    ICCI, 1993, pp:565-569 [Conf]
  20. C. Y. Roger Chen
    TOBOL - a new methodology for the top-to-bottom level hardware description in VLSI design-automation systems. [Citation Graph (0, 0)][DBLP]
    ICCL, 1988, pp:404-411 [Conf]
  21. C. Y. Roger Chen, Yeh-Ching Chung
    Embedding Networks with Ring Connections in Hypercube Machines. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:327-334 [Conf]
  22. Calvin J. A. Hsia, C. Y. Roger Chen
    Permutation Capability of Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:338-346 [Conf]
  23. Dikran S. Meliksetian, C. Y. Roger Chen
    Communication Aspects of the Cube Connected Cycles. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:579-580 [Conf]
  24. Muhammad F. Mudawwar, C. Y. Roger Chen
    The Signal Flow Model: A novel Data Driven Approach to Parallel Processing. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:196-200 [Conf]
  25. Shuo-Hsien Hsiao, C. Y. Roger Chen
    A New Model for the Performance Evaluation of Synchronous Circuit Switched Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:773-777 [Conf]
  26. Calvin J. A. Hsia, C. Y. Roger Chen
    Synthesis of Asynchronous Circuits - Testing Unique Circuit Behavior of Signal Transition Graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1074-1077 [Conf]
  27. Naresh Kumar Seghal, C. Y. Roger Chen, John M. Acken
    A High Performance General Purpose Multi-Point Signal Router. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:475-478 [Conf]
  28. Bill Halpin, Naresh Sehgal, C. Y. Roger Chen
    Detailed Placement with Net Length Constraints. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:22-27 [Conf]
  29. Abdulaziz S. Mazyad, C. Y. Roger Chen
    Performance Evaluation of HIPPI Interconnection System Using a Camp-On Strategy. [Citation Graph (0, 0)][DBLP]
    LCN, 1994, pp:20-29 [Conf]
  30. Dikran S. Meliksetian, C. Y. Roger Chen
    Performance Analysis of Communications in Static Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1992, pp:249-250 [Conf]
  31. Dikran S. Meliksetian, C. Y. Roger Chen
    A Markov-Modulated Bernoulli Process Approximation for the Analysis of Banyan Networks. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1993, pp:183-194 [Conf]
  32. Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
    Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:53-58 [Conf]
  33. P. Bruce Berra, C. Y. Roger Chen, Arif Ghafoor, C. C. Lin, Thomas D. C. Little, D. Shin
    Architecture for distributed multimedia database systems. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1990, v:13, n:4, pp:217-231 [Journal]
  34. Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian
    Transistor Chaining in Static CMOS Functional Cells of Arbitrary Planar Topology. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 1999, v:90, n:1-3, pp:89-114 [Journal]
  35. Kingsley C. Nwosu, C. Y. Roger Chen, P. Bruce Berra
    Multimedia Object Modeling and Storage Allocation Strategies. [Citation Graph (0, 0)][DBLP]
    J. Intell. Inf. Syst., 1994, v:3, n:3/4, pp:357-398 [Journal]
  36. Arif Ghafoor, C. Y. Roger Chen
    Special Issue on Multimedia Processing and Technology. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:30, n:2, pp:107-110 [Journal]
  37. C. Y. Roger Chen, Dikran S. Meliksetian, M. C. Chang, L. J. Liu
    Design of a Multimedia Object-Oriented DBMS. [Citation Graph (0, 0)][DBLP]
    Multimedia Syst., 1995, v:3, n:5-6, pp:217-227 [Journal]
  38. Bradley S. Carlson, C. Y. Roger Chen, Dikran S. Meliksetian
    Dual Eulerian Properties of Plane Multigraphs. [Citation Graph (0, 0)][DBLP]
    SIAM J. Discrete Math., 1995, v:8, n:1, pp:33-50 [Journal]
  39. Bradley S. Carlson, C. Y. Roger Chen, Uminder Singh
    Optimal cell generation for dual independent layout styles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:6, pp:770-782 [Journal]
  40. C. Y. Roger Chen, Cliff Yungchin Hou, Bradley S. Carlson
    A preprocessor for improving channel routing hierarchical pin permutation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:7, pp:896-903 [Journal]
  41. C. Y. Roger Chen, Cliff Yungchin Hou, Uminder Singh
    Optimal algorithms for bubble sort based non-Manhattan channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:603-609 [Journal]
  42. C. Y. Roger Chen, Michael Z. Moricz
    A delay distribution methodology for the optimal systolic synthesis of linear recurrence algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:6, pp:685-697 [Journal]
  43. C. Y. Roger Chen, Cliff Yungchin Hou
    A pin permutation algorithm for improving over-the-cell channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:1030-1037 [Journal]
  44. Uminder Singh, C. Y. Roger Chen
    From logic to symbolic layout for gate matrix. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:216-227 [Journal]
  45. Qinghong Wu, C. Y. Roger Chen, Bradley S. Carlson
    LILA: layout generation for iterative logic arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1359-1369 [Journal]
  46. Muhammad Naeem Ayyaz, Dikran S. Meliksetian, C. Y. Roger Chen
    Partitionable multistage interconnection networks. Part 2: Task migration schemes. [Citation Graph (0, 0)][DBLP]
    Telecommunication Systems, 2000, v:13, n:1, pp:45-67 [Journal]
  47. Muhammad Naeem Ayyaz, Dikran S. Meliksetian, C. Y. Roger Chen
    Partitionable multistage interconnection networks. Part 1: Dynamic subcube compaction. [Citation Graph (0, 0)][DBLP]
    Telecommunication Systems, 1998, v:10, n:1, pp:79-106 [Journal]
  48. Dikran S. Meliksetian, Frank Feng-Kuo Yu, C. Y. Roger Chen
    Methodologies for Designing Video Servers. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Multimedia, 2000, v:2, n:1, pp:62-69 [Journal]
  49. C. Y. Roger Chen, Shuo-Hsien Hsiao, Abdulaziz S. Almazyad
    A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 1995, v:3, n:6, pp:708-715 [Journal]
  50. C. Y. Roger Chen, Georges A. Makhoul, Dikran S. Meliksetian
    A queueing analysis of the performance of DQDB. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 1995, v:3, n:6, pp:872-881 [Journal]
  51. James V. Luciani, C. Y. Roger Chen
    An analytical model for partially blocking finite-buffered switching networks. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 1994, v:2, n:5, pp:533-540 [Journal]
  52. Shuo-Hsien Hsiao, C. Y. Roger Chen
    Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:5, pp:632-640 [Journal]
  53. Dikran S. Meliksetian, C. Y. Roger Chen
    Optimal Routing Algorithm and the Diameter of the Cube-Connected Cycles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:10, pp:1172-1178 [Journal]

  54. A new technique for exploiting regularity in data path synthesis. [Citation Graph (, )][DBLP]


  55. A technique for selecting CMOS transistor orders. [Citation Graph (, )][DBLP]


  56. Algorithms to simplify multi-clock/edge timing constraints. [Citation Graph (, )][DBLP]


  57. An efficient gate delay model for VLSI design. [Citation Graph (, )][DBLP]


  58. Modeling and reduction of complex timing constraints in high performance digital circuits. [Citation Graph (, )][DBLP]


  59. Performance analysis of single-buffered multistage interconnection networks. [Citation Graph (, )][DBLP]


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