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Stephen T. Quay: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Buffer Insertion for Noise and Delay Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:362-367 [Conf]
  2. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Buffer Insertion with Accurate Gate and Interconnect Delay Computation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:479-484 [Conf]
  3. Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay
    Fast and flexible buffer trees that navigate the physical layout environment. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:24-29 [Conf]
  4. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Is wire tapering worthwhile? [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:430-436 [Conf]
  5. José Luis Neves, Stephen T. Quay
    Buffer Library Selection. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:221-226 [Conf]
  6. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
    Steiner tree optimization for buffers. Blockages and bays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:399-402 [Conf]
  7. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:104-109 [Conf]
  8. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay
    Porosity aware buffered steiner tree construction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:158-165 [Conf]
  9. Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
    Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:4-9 [Conf]
  10. Charles J. Alpert, Milos Hrkic, Stephen T. Quay
    A fast algorithm for identifying good buffer insertion candidate locations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:47-52 [Conf]
  11. Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
    Buffer insertion with adaptive blockage avoidance. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:92-97 [Conf]
  12. Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi
    Probabilistic Congestion Prediction with Partial Blockages. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:841-846 [Conf]
  13. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:136-141 [Journal]
  14. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
    Interconnect synthesis without wire tapering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:90-104 [Journal]
  15. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
    Correction to "interconnect synthesis without wire tapering". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:497-497 [Journal]
  16. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Buffer insertion for noise and delay optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1633-1645 [Journal]
  17. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze
    Porosity-aware buffered Steiner tree construction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:517-526 [Journal]
  18. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
    Steiner tree optimization for buffers, blockages, and bays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:556-562 [Journal]
  19. Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
    Buffer insertion with adaptive blockage avoidance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:492-498 [Journal]
  20. Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
    The nuts and bolts of physical synthesis. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:89-94 [Conf]

  21. Fast Electrical Correction Using Resizing and Buffering. [Citation Graph (, )][DBLP]


  22. Fast interconnect synthesis with layer assignment. [Citation Graph (, )][DBLP]


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