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Publications of Author

1. Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   HSIS: A BDD-Based Environment for Formal Verification. [Citation Graph (0, 0)][DBLP]
   DAC, 1994, pp:454-459 [Conf]
   
2. Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem
   Coordinated transformations for high-level synthesis of high performance microprocessor blocks. [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:898-903 [Conf]
   
3. Yatin Vasant Hoskote, Timothy Kam, Pei-Hsin Ho, Xudong Zhao
   Coverage Estimation for Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:300-305 [Conf]
   
4. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
   A Fully Implicit Algorithm for Exact State Minimization. [Citation Graph (0, 0)][DBLP]
   DAC, 1994, pp:684-690 [Conf]
   
5. Alan Mishchenko, Xinning Wang, Timothy Kam
   A new enhanced constructive decomposition and mapping algorithm. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:143-148 [Conf]
   
6. Yirng-An Chen, Edmund M. Clarke, Pei-Hsin Ho, Yatin Vasant Hoskote, Timothy Kam, Manpreet Khaira, John W. O'Leary, Xudong Zhao
   Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking. [Citation Graph (0, 0)][DBLP]
   FMCAD, 1996, pp:19-33 [Conf]
   
7. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam
   Reducing structural bias in technology mapping. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:519-526 [Conf]
   
8. Pei-Hsin Ho, Adrian J. Isles, Timothy Kam
   Formal verification of pipeline control using controlled token nets and abstract interpretation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1998, pp:529-536 [Conf]
   
9. Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton
   Algorithms for Discrete Function Manipulation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1990, pp:92-95 [Conf]
   
10. Timothy Kam, P. A. Subrahmanyam
    Comparing Layouts with HDL Models: A Formal Verification Technique. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:588-591 [Conf]
    
11. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Implicit state minimization of non-deterministic FSMs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:250-257 [Conf]
    
12. Timothy Kam, P. A. Subrahmanyam
    Comparing layouts with HDL models: a formal verification technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:503-509 [Journal]
    
13. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Implicit computation of compatible sets for state minimization of ISFSMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:657-676 [Journal]
    
14. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Theory and algorithms for state minimization of nondeterministic FSMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1311-1322 [Journal]
    
15. Tiziano Villa, Timothy Kam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Explicit and implicit algorithms for binate covering problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:677-691 [Journal]
    
16. 
    Automatic multithreaded pipeline synthesis from transactional datapath specifications. [Citation Graph (, )][DBLP]
    
    
17. 
    Automatic pipelining from transactional datapath specifications. [Citation Graph (, )][DBLP]
    
    
18. 
    Correct-by-construction microarchitectural pipelining. [Citation Graph (, )][DBLP]
    
    
19. 
    A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. [Citation Graph (, )][DBLP]