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Milos Hrkic: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay
    Fast and flexible buffer trees that navigate the physical layout environment. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:24-29 [Conf]
  2. Milos Hrkic, John Lillis
    S-Tree: a technique for buffered routing tree synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:578-583 [Conf]
  3. Milos Hrkic, John Lillis, Giancarlo Beraudo
    An approach to placement-coupled logic replication. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:711-716 [Conf]
  4. Hosung (Leo) Kim, John Lillis, Milos Hrkic
    Techniques for improved placement-coupled logic replication. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:211-216 [Conf]
  5. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:104-109 [Conf]
  6. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay
    Porosity aware buffered steiner tree construction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:158-165 [Conf]
  7. Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
    Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:4-9 [Conf]
  8. Charles J. Alpert, Milos Hrkic, Stephen T. Quay
    A fast algorithm for identifying good buffer insertion candidate locations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:47-52 [Conf]
  9. Milos Hrkic, John Lillis
    Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:98-103 [Conf]
  10. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:136-141 [Journal]
  11. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze
    Porosity-aware buffered Steiner tree construction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:517-526 [Journal]
  12. Milos Hrkic, John Lillis
    Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:481-491 [Journal]
  13. Milos Hrkic, John Lillis, Giancarlo Beraudo
    An Approach to Placement-Coupled Logic Replication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2539-2551 [Journal]

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