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Mustafa Badaroglu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
    Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:399-404 [Conf]
  2. Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens
    High-level simulation of substrate noise generation including power supply noise coupling. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:446-451 [Conf]
  3. Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:854-859 [Conf]
  4. Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens
    High-level simulation of substrate noise generation from large digital circuits with multiple supplies. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:326-330 [Conf]
  5. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Digital Ground Bounce Reduction by Phase Modulation of the Clock. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:88-93 [Conf]
  6. Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1146-1154 [Journal]
  7. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Digital ground bounce reduction by supply current shaping and clock frequency Modulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:65-76 [Journal]
  8. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    SWAN: high-level simulation methodology for digital substrate noise generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:23-33 [Journal]
  9. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Scalable Gate-Level Models for Power and Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2938-2941 [Conf]

  10. Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment. [Citation Graph (, )][DBLP]


  11. Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers. [Citation Graph (, )][DBLP]


  12. A Cascadable Random Neural Network Chip with Reconfigurable Topology. [Citation Graph (, )][DBLP]


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