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Piet Wambacq: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
    Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:399-404 [Conf]
  2. Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:854-859 [Conf]
  3. Gerd Vandersteen, Piet Wambacq, Yves Rolain, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens
    A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:440-445 [Conf]
  4. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Digital Ground Bounce Reduction by Phase Modulation of the Clock. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:88-93 [Conf]
  5. Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay
    Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10624-10629 [Conf]
  6. Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10642-10649 [Conf]
  7. Michaël Goffioul, Piet Wambacq, Gerd Vandersteen, Stéphane Donnay
    Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach . [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:352-356 [Conf]
  8. Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
    Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:270-275 [Conf]
  9. Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Frans Verbeyst
    High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:586-591 [Conf]
  10. Gerd Vandersteen, Piet Wambacq, Yves Rolain, Johan Schoukens, Stéphane Donnay, Marc Engels, Ivo Bolsens
    Efficient bit-error-rate estimation of multicarrier transceivers. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:164-168 [Conf]
  11. Piet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens
    Compact Modeling of Nonlinear Distortion in Analog Communication Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:350-0 [Conf]
  12. Piet Wambacq, Stéphane Donnay, Hocine Ziad, Marc Engels, Hugo De Man, Ivo Bolsens
    A Single-Package Solution for Wireless Transceivers. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:425-0 [Conf]
  13. Piet Wambacq, Gerd Vandersteen, Joel R. Phillips, Jaijeet S. Roychowdhury, Wolfgang Eberle, Baolin Yang, David E. Long, Alper Demir
    CAD for RF circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:520-529 [Conf]
  14. Christiaan Fivez, Piet Wambacq, Emiel Schoeters, André Oosterlinck, Piet Vuylsteke
    A Novel Method for Scattered Radiation Compensation in X-Ray Imaging Systems, Using Partially Transparent Shields (PTS). [Citation Graph (0, 0)][DBLP]
    ICIP (3), 1994, pp:701-705 [Conf]
  15. Francisco V. Fernández, Piet Wambacq, Georges G. E. Gielen, Ángel Rodríguez-Vázquez, Willy M. C. Sansen
    Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:25-28 [Conf]
  16. Georges G. E. Gielen, Geert Debyser, Piet Wambacq, Koen Swings, Willy M. C. Sansen
    Use of Symbolic Analysis in Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2205-2208 [Conf]
  17. Ralf Brederlow, Werner Weber, Joseph Sauerer, Stéphane Donnay, Piet Wambacq, Maarten Vertregt
    A Mixed-Signal Design Roadmap. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:6, pp:34-46 [Journal]
  18. Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1146-1154 [Journal]
  19. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Digital ground bounce reduction by supply current shaping and clock frequency Modulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:65-76 [Journal]
  20. Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay
    Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1215-1227 [Journal]
  21. Manuel Innocent, Piet Wambacq, Stéphane Donnay, Harrie A. C. Tilmans, Willy M. C. Sansen, Hugo De Man
    An analytic Volterra-series-based model for a MEMS variable capacitor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:124-131 [Journal]
  22. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    SWAN: high-level simulation methodology for digital substrate noise generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:23-33 [Journal]
  23. Jonathan Borremans, Ludwig De Locht, Piet Wambacq, Yves Rolain
    Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:261-266 [Conf]
  24. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Scalable Gate-Level Models for Power and Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2938-2941 [Conf]
  25. Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay
    Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  26. Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications. [Citation Graph (, )][DBLP]


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