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Mary L. Bailey :
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Mary L. Bailey , Lawrence Snyder An Empirical Study of On-chip Parallelism. [Citation Graph (0, 0)][DBLP ] DAC, 1988, pp:160-165 [Conf ] Prasenjit Sarkar , Mary L. Bailey CNI: A High-Performance Network Interface for Workstation Clusters. [Citation Graph (0, 0)][DBLP ] HPDC, 1996, pp:151-160 [Conf ] Mary L. Bailey , David Socha , David Notkin Debugging Parallel Programs using Graphical Views. [Citation Graph (0, 0)][DBLP ] ICPP (2), 1988, pp:46-49 [Conf ] Yi-Bing Lin , Edward D. Lazowska , Mary L. Bailey Comparing Synchronization Protocols for Parallel Logic-Level Simulation. [Citation Graph (0, 0)][DBLP ] ICPP (3), 1990, pp:223-227 [Conf ] Mary L. Bailey , Burra Gopal , Michael A. Pagels , Larry L. Peterson , Prasenjit Sarkar PathFinder: A Pattern-Based Packet Classifier. [Citation Graph (0, 0)][DBLP ] OSDI, 1994, pp:115-123 [Conf ] David Socha , Mary L. Bailey , David Notkin Voyeur: Graphical Views of Parallel Programs. [Citation Graph (0, 0)][DBLP ] Workshop on Parallel and Distributed Debugging, 1988, pp:206-216 [Conf ] David Notkin , Lawrence Snyder , David Socha , Mary L. Bailey , Bruce Forstall , Kevin Gates , Raymond Greenlaw , William G. Griswold , Thomas J. Holman , Richard Korry , Gemini Lasswell , Robert Mitchell , Philip A. Nelson Experiences with Poker. [Citation Graph (0, 0)][DBLP ] PPOPP/PPEALS, 1988, pp:10-20 [Conf ] Mary L. Bailey , Shane Walker Towards "on the fly" performance models for conservative asynchronous protocols. [Citation Graph (0, 0)][DBLP ] Winter Simulation Conference, 1994, pp:1431-1434 [Conf ] Mary L. Bailey , Michael A. Pagels Measuring the overhead in conservative parallel simulations of multicomputer programs. [Citation Graph (0, 0)][DBLP ] Winter Simulation Conference, 1991, pp:627-636 [Conf ] Wilkey Richardson , Mary L. Bailey , William H. Sanders Using ZPL to Develop a Parallel Chaos Router Simulator. [Citation Graph (0, 0)][DBLP ] Winter Simulation Conference, 1996, pp:809-816 [Conf ] Mary L. Bailey , Jack V. Briner Jr. , Roger D. Chamberlain Parallel Logic Simulation of VLSI Systems. [Citation Graph (0, 0)][DBLP ] ACM Comput. Surv., 1994, v:26, n:3, pp:255-294 [Journal ] Mary L. Bailey How circuit size affects parallelism. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:208-215 [Journal ] Mary L. Bailey A time-based model for investigating parallel logic-level simulation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:816-824 [Journal ] Mary L. Bailey A delay-based model for circuit parallelism. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1903-1912 [Journal ] Prasenjit Sarkar , Mary L. Bailey Adapting the Network Interface for High-Performance Computing: The CNI Approach. [Citation Graph (0, 0)][DBLP ] The Journal of Supercomputing, 1997, v:11, n:2, pp:181-200 [Journal ] Mary L. Bailey , Michael A. Pagels Empirical Measurements of Overheads in Conservative Asynchronous Simulations. [Citation Graph (0, 0)][DBLP ] ACM Trans. Model. Comput. Simul., 1994, v:4, n:4, pp:350-367 [Journal ] Tony DeRose , Mary L. Bailey , Bill Barnard , Robert Cypher , David Dobrikin , Carl Ebeling , Smaragda Konstantinidou , Larry McMurchie , Haim Mizrahi , Bill Yost Apex: two architectures for generating parametric curves and surfaces. [Citation Graph (0, 0)][DBLP ] The Visual Computer, 1989, v:5, n:5, pp:264-276 [Journal ] Search in 0.002secs, Finished in 0.003secs