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Cyrus Bamji: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cyrus Bamji, Jonathan Allen
    GRASP: A Grammar-based Schematic Parser. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:448-453 [Conf]
  2. Cyrus Bamji, Enrico Malavasi
    Enhanced Network Flow Algorithm for Yield Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:746-751 [Conf]
  3. Cyrus Bamji, Ravi Varadarajan
    Hierarchical Pitchmatching Compaction Using Minimum Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:311-317 [Conf]
  4. Cyrus Bamji, Ravi Varadarajan
    MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:389-394 [Conf]
  5. Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah
    Functional Timing Analysis for IP Characterization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:731-736 [Conf]
  6. Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
    An Advanced Timing Characterization Method Using Mode Dependency. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:657-660 [Conf]
  7. Cyrus Bamji, Charles E. Hauck, Jonathan Allen
    A design by example regular structure generator. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:16-22 [Conf]
  8. Pawan Kulshreshtha, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin
    Transistor-Level Timing Analysis Using Embedded Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:344-348 [Conf]
  9. Ravi Varadarajan, Cyrus Bamji
    Cloning techniques for hierarchical compaction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:158-161 [Conf]
  10. Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar
    Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:130-135 [Conf]
  11. Cyrus Bamji, Jonathan Allen
    GLOVE: A Graph-Based Layout Verifier. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:215-220 [Conf]
  12. Cyrus Bamji, Manjit Borah
    An Improved Cost Heuristic for Transistor Sizing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:534-0 [Conf]
  13. Cyrus Bamji, Ravi Varadarajan
    Incremental Autojogging using Range Spaces. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:265-0 [Conf]
  14. Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
    Fast and accurate timing characterization using functionalinformation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:315-331 [Journal]
  15. Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
    Interleaving buffer insertion and transistor sizing into a single optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:625-633 [Journal]
  16. Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
    Technology mapping for high-performance static CMOS and pass transistor logic designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:577-589 [Journal]

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