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Publications of Author

1. Ansuman Banerjee, Bhaskar Pal, Sayantan Das, Abhijeet Kumar, Pallab Dasgupta
   Test generation games from formal specifications. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:827-832 [Conf]
   
2. Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti, Ansuman Banerjee
   Formal verification of module interfaces against real time specifications. [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:141-145 [Conf]
   
3. Sayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni
   Formal verification coverage: computing the coverage gap between temporal specifications. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2004, pp:198-203 [Conf]
   
4. Ansuman Banerjee, Pallab Dasgupta, Partha Pratim Chakrabarti
   Open computation tree logic with fairness. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:249-252 [Conf]
   
5. Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
   The BUSpec platform for automated generation of verification aids for standard bus protocols. [Citation Graph (0, 0)][DBLP]
   MEMOCODE, 2004, pp:119-128 [Conf]
   
6. Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
   Formal Verification of Modules under Real Time Environment Constraints. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2004, pp:103-108 [Conf]
   
7. Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix
   Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:201-206 [Conf]
   
8. Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni
   Design-Intent Coverage - A New Paradigm for Formal Property Verification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1922-1934 [Journal]
   
9. Ansuman Banerjee, Pallab Dasgupta
   The open family of temporal logics: Annotating temporal operators with input constraints. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:492-522 [Journal]
   
10. Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
    Formal methods for checking realizability of coalitions in 3-party systems. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:198- [Conf]
    
11. Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
    BUSpec: A framework for generation of verification aids for standard bus protocol specifications. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:285-304 [Journal]
    
12. 
    CheckSpec: A Tool for Consistency and Coverage Analysis of Assertion Specifications. [Citation Graph (, )][DBLP]
    
    
13. 
    A Dynamic Assertion-Based Verification Platform for Validation of UML Designs. [Citation Graph (, )][DBLP]
    
    
14. 
    Cohesive Coverage Management for Simulation and Formal Property Verification. [Citation Graph (, )][DBLP]
    
    
15. 
    Synthesizability of 3 Party Formal Specifications-Does My Controller See Enough?. [Citation Graph (, )][DBLP]