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Leendert M. Huisman: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
    SLS - a fast switch level simulator for verification and fault coverage analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:164-170 [Conf]
  2. Thomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski
    Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:287-296 [Conf]
  3. Leendert M. Huisman
    Correlations between path delays and the accuracy of performance prediction. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:801-808 [Conf]
  4. Leendert M. Huisman, Larry Carter, Tom W. Williams
    TRIM : Testability Range by Ignoring the Memory. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:474-479 [Conf]
  5. Leendert M. Huisman, Maroun Kassab, Leah Pastel
    Data Mining Integrated Circuit Fails with Fail Commonalities. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:661-668 [Conf]
  6. Daniel R. Knebel, Pia Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika
    Diagnosis and characterization of timing-related defects by time-dependent light emission. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:733-739 [Conf]
  7. Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy
    A Small Test Generator for Large Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:30-40 [Conf]
  8. Peter C. Maxwell, Robert C. Aitken, Leendert M. Huisman
    The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:739-746 [Conf]
  9. Peter Wohl, Leendert M. Huisman
    Analysis and Design of Optimal Combinational Compactors. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:101-106 [Conf]
  10. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman
    Using a Hardware Simulation Engine for Custom MOS Structured Designs. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1984, v:28, n:5, pp:564-571 [Journal]
  11. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
    SLS-a fast switch-level simulator [for MOS]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:838-849 [Journal]
  12. Larry Carter, Leendert M. Huisman, Tom W. Williams
    TRIM: testability range by ignoring the memory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:38-49 [Journal]
  13. Leendert M. Huisman
    Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:91-101 [Journal]
  14. Leendert M. Huisman, Sandip Kundu
    Highly Reliable Symmetric Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:1, pp:94-97 [Journal]

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