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Vijay S. Iyengar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
    SLS - a fast switch level simulator for verification and fault coverage analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:164-170 [Conf]
  2. Vijay S. Iyengar, David Flaxer, Anil Nigam, John Vergo
    Evaluation of IT Portfolio Options by Linking to Business Services. [Citation Graph (0, 0)][DBLP]
    DEECS, 2006, pp:66-80 [Conf]
  3. Vijay S. Iyengar, Louise Trevillyan, Pradip Bose
    Representative Traces for Processor Models with Infinite Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:62-72 [Conf]
  4. Daniel Brand, Vijay S. Iyengar
    Identification of Single Gate Delay Fault Redundancies. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:24-28 [Conf]
  5. Ashok K. Chandra, Vijay S. Iyengar
    Constraint Slving for Test Case Generation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:245-248 [Conf]
  6. Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen
    Architectural Verification of Processors Using Symbolic Instruction Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:454-459 [Conf]
  7. Vijay S. Iyengar
    HOT: Heuristics for Oblique Trees. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1999, pp:91-98 [Conf]
  8. Yaron Aizenbud, Paul Chang, Moshe Leibowitz, Dave Smith, Bernd Könemann, Vijay S. Iyengar, Barry K. Rosen
    AC Test Quality: Beyond Transition Fault Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:568-577 [Conf]
  9. Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman
    Efficient Fault Simulation of CMOS Circuits with Accurate Models. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:520-529 [Conf]
  10. Zeev Barzilai, Vijay S. Iyengar, Barry K. Rosen, Gabriel M. Silberman
    Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:722-731 [Conf]
  11. Daniel Brand, Vijay S. Iyengar
    Synthesis of Pseudo-Random Pattern Testable Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:501-508 [Conf]
  12. Vijay S. Iyengar, Larry L. Kinney
    Concurrent Testing of Flow of Control in Simple Microprogrammed Control Units. [Citation Graph (0, 0)][DBLP]
    ITC, 1982, pp:469-479 [Conf]
  13. Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
    Delay Test Generation 1: Concepts and Coverage Metrics. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:857-866 [Conf]
  14. Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
    Delay Test Generation 2: Algebra and Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:867-876 [Conf]
  15. Vijay S. Iyengar, Gopalakrishnan Vijayan
    Test Application Timing: The Unexplored Issue in AC Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:840-847 [Conf]
  16. Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams
    Delay Test: The Next Frontier for LSSD Test Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:578-587 [Conf]
  17. Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy
    A Small Test Generator for Large Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:30-40 [Conf]
  18. John A. Waicukauski, Eric Lindbloom, Vijay S. Iyengar, Barry K. Rosen
    Transition Fault Simulation by Parallel Pattern Single Fault Propagation. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:542-551 [Conf]
  19. Vijay S. Iyengar
    Transforming data to satisfy privacy constraints. [Citation Graph (0, 0)][DBLP]
    KDD, 2002, pp:279-288 [Conf]
  20. Vijay S. Iyengar
    On detecting space-time clusters. [Citation Graph (0, 0)][DBLP]
    KDD, 2004, pp:587-592 [Conf]
  21. Vijay S. Iyengar, Chidanand Apté, Tong Zhang
    Active learning using adaptive resampling. [Citation Graph (0, 0)][DBLP]
    KDD, 2000, pp:91-98 [Conf]
  22. Vijay S. Iyengar, Tong Zhang
    Empirical Study of Recommender Systems Using Linear Classifiers. [Citation Graph (0, 0)][DBLP]
    PAKDD, 2001, pp:16-27 [Conf]
  23. Vijay S. Iyengar, Jon Lee, Murray Campbell
    Evaluating multiple attribute items using queries. [Citation Graph (0, 0)][DBLP]
    ACM Conference on Electronic Commerce, 2001, pp:144-153 [Conf]
  24. Tong Zhang, Vijay S. Iyengar
    Recommender Systems Using Linear Classifier. [Citation Graph (0, 0)][DBLP]
    Journal of Machine Learning Research, 2002, v:2, n:, pp:313-334 [Journal]
  25. Daniel Brand, Vijay S. Iyengar
    Timing Analysis Using Functional Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:10, pp:1309-1315 [Journal]
  26. Vijay S. Iyengar, Larry L. Kinney
    Concurrent Fault Detection in Microprogrammed Control Units. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:9, pp:810-821 [Journal]
  27. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
    SLS-a fast switch-level simulator [for MOS]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:838-849 [Journal]
  28. Daniel Brand, Vijay S. Iyengar
    Identification of redundant delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:553-565 [Journal]
  29. Vijay S. Iyengar, Barry K. Rosen, John A. Waicukauski
    On computing the sizes of detected delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:3, pp:299-312 [Journal]
  30. Vijay S. Iyengar, Gopalakrishnan Vijayan
    Optimized test application timing for AC test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1439-1449 [Journal]
  31. Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal
    AVPGEN-A test generator for architecture verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:188-200 [Journal]

  32. Analytics for Audit and Business Controls in Corporate Travel and Entertainment. [Citation Graph (, )][DBLP]


  33. Event detection in sensor networks for modern oil fields. [Citation Graph (, )][DBLP]


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